From: Konstantinos Margaritis Date: Wed, 27 Jul 2022 13:18:13 +0000 (+0000) Subject: Fix fmvis & fishmv bit handling for d0, add tests for negative fp numbers X-Git-Tag: sv_maxu_works-initial~212 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04f20aaff9ad03410dd7c6f483a50c754667f99c;p=openpower-isa.git Fix fmvis & fishmv bit handling for d0, add tests for negative fp numbers --- diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 6c3e032f..a3a5245c 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -336,20 +336,20 @@ def fmvis(fields): # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG # V3.0B 1.6.6 DX-FORM # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 | - # | PO | FRS | d1 | d0 | XO |d2 | + # | PO | FRS | d1 | d0 | XO |d2 | PO = 22 XO = 0b00011 (FRS, imm) = fields # first split imm into d1, d0 and d2. sigh d2 = (imm & 1) # LSB (0) d1 = (imm >> 1) & 0b11111 # bits 1-5 - d0 = (imm >> 5) # MSBs 6-15 + d0 = (imm >> 6) # MSBs 6-15 return instruction( (PO , 0 , 5), (FRS, 6 , 10), (d1, 11, 15), - (d0, 16, 26), - (XO , 27, 30), + (d0, 16, 25), + (XO , 26, 30), (d2 , 31, 31), ) @@ -357,23 +357,21 @@ def fmvis(fields): def fishmv(fields): # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG # V3.0B 1.6.6 DX-FORM - # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 | - # | PO | FRS | d1 | d0 | XO |d2 | + # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 | + # | PO | FRS | d1 | d0 | XO |d2 | PO = 22 XO = 0b01011 (FRS, imm) = fields # first split imm into d1, d0 and d2. sigh d2 = (imm & 1) # LSB (0) d1 = (imm >> 1) & 0b11111 # bits 1-5 - d0 = (imm >> 5) # MSBs 6-15 - print("imm", hex(imm)) - print("d0 d1 d2", hex(d0), hex(d1), hex(d2)) + d0 = (imm >> 6) # MSBs 6-15 return instruction( (PO , 0 , 5), (FRS, 6 , 10), (d1, 11, 15), - (d0, 16, 26), - (XO , 27, 30), + (d0, 16, 25), + (XO , 26, 30), (d2 , 31, 31), ) diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py index 2ddaf207..de03d8b7 100644 --- a/src/openpower/test/alu/fmvis_cases.py +++ b/src/openpower/test/alu/fmvis_cases.py @@ -16,6 +16,7 @@ class FMVISTestCase(TestAccumulatorBase): lst = SVP64Asm(["fmvis 5, 0x4000", # 2.0 "fmvis 6, 0x4048", # 3.125 "fmvis 7, 0x3E80", # 0.25 + "fmvis 8, 0xc048", # -3.125 ]) lst = list(lst) @@ -23,7 +24,8 @@ class FMVISTestCase(TestAccumulatorBase): expected_fprs[5] = 0x4000000000000000 # 2.0 in FP64 form expected_fprs[6] = 0x4009000000000000 # 3.125 in FP64 form expected_fprs[7] = 0x3FD0000000000000 # 0.25 in FP64 form - e = ExpectedState(pc=0xc, # 3 instructions so 3x4=0xc + expected_fprs[8] = 0xC009000000000000 # -3.125 in FP64 form + e = ExpectedState(pc=0x10, # 4 instructions so 4x4=0x10 fp_regs=expected_fprs) # expected results self.add_case(Program(lst, bigendian), expected=e) @@ -31,13 +33,16 @@ class FMVISTestCase(TestAccumulatorBase): lst = SVP64Asm(["fmvis 3, 0x4049", # 1st half of 3.14159 in FP32 form "fishmv 3, 0x0FD0", # 2nd half of 3.14159 in FP32 form - "fmvis 5, 0x3F80", # 1st half of 1.00195 in FP32 form - "fishmv 5, 0x4000", # 2nd half of 1.00195 in FP32 form + "fmvis 4, 0x3F80", # 1st half of 1.00195 in FP32 form + "fishmv 4, 0x4000", # 2nd half of 1.00195 in FP32 form + "fmvis 5, 0xC049", # 1st half of -3.14159 in FP32 form + "fishmv 5, 0x0FD0", # 2nd half of -3.14159 in FP32 form ]) lst = list(lst) expected_fprs = [0] * 32 expected_fprs[3] = 0x400921fa00000000 # 3.14159 in FP64 form - expected_fprs[5] = 0x3ff0080000000000 # 1.00195 in FP64 form - e = ExpectedState(pc=0x10, fp_regs=expected_fprs) + expected_fprs[4] = 0x3ff0080000000000 # 1.00195 in FP64 form + expected_fprs[5] = 0xC00921fa00000000 # -3.14159 in FP64 form + e = ExpectedState(pc=0x18, fp_regs=expected_fprs) self.add_case(Program(lst, bigendian), expected=e)