From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Jun 2021 14:34:43 +0000 (+0100)
Subject: use new PowerOp.like function in PowerDecoder, fix missing fields
X-Git-Tag: xlen-bcd~394
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04f6883cb511fbcb154a22fb6b8cb9949b49af9a;p=openpower-isa.git

use new PowerOp.like function in PowerDecoder, fix missing fields
---

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 22907324..8d7fcfa9 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -183,7 +183,7 @@ class PowerOp:
         self.name = name
         self.subset = subset
         if fields is not None:
-            for k, v in fields:
+            for k, v in fields.items():
                 setattr(self, k, v)
             return
         debug_report = set()
@@ -214,8 +214,9 @@ class PowerOp:
         """
         fields = {}
         for fname in other._fields:
-            sig = getattr(other, fname)
-            fields[fname] = sig.__class__.like(sig)
+            sig = getattr(other, fname, None)
+            if sig is not None:
+                fields[fname] = sig.__class__.like(sig)
         return PowerOp(subset=other.subset, fields=fields)
 
     def _eq(self, row=None):
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 10906ede..9d26e677 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -25,7 +25,8 @@ from openpower.sv.svp64 import SVP64Rec
 
 from openpower.decoder.power_regspec_map import regspec_decode_read
 from openpower.decoder.power_decoder import (create_pdecode,
-                                             create_pdecode_svp64_ldst,)
+                                             create_pdecode_svp64_ldst,
+                                             PowerOp)
 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
                                      CRInSel, CROutSel,
                                      LdstLen, In1Sel, In2Sel, In3Sel,
@@ -788,6 +789,9 @@ class PowerDecodeSubset(Elaboratable):
                                               row_subset=self.rowsubsetfn)
             self.svdecldst = svdecldst
 
+        # set up a copy of the PowerOp
+        self.op = PowerOp.like(self.dec.op)
+
         # state information needed by the Decoder
         if state is None:
             state = CoreState("dec2")
@@ -875,6 +879,10 @@ class PowerDecodeSubset(Elaboratable):
         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec, op)
 
+        # use op from first decoder (self.dec.op) if not in SVP64-LDST mode
+        # (TODO)
+        comb += self.op.eq(self.dec.op)
+
         if self.svp64_en:
             # and SVP64 RM mode decoder
             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
@@ -1104,7 +1112,7 @@ class PowerDecode2(PowerDecodeSubset):
         m = super().elaborate(platform)
         comb = m.d.comb
         state = self.state
-        e_out, op, do_out = self.e, self.dec.op, self.e.do
+        op, e_out, do_out = self.op, self.e, self.e.do
         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
         rc_out = self.dec_rc.rc_out.data
         e = self.e_tmp