From: Ron Dreslinski <rdreslin@umich.edu>
Date: Wed, 11 Oct 2006 04:19:31 +0000 (-0400)
Subject: When turning asserts into if's don't forget to invert.
X-Git-Tag: m5_2.0_beta2~104^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04f71f1226d0eb20694806b2a3b2546238eb4f5b;p=gem5.git

When turning asserts into if's don't forget to invert.

src/mem/cache/base_cache.cc:
    When turning asserts into if's don't forget to invert.
    Must be too sleepy.

--HG--
extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
---

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 8b724209e..328e1c7cc 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -135,7 +135,7 @@ BaseCache::CachePort::recvRetry()
     else if (!isCpuSide)
     {
         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
-        if (cache->doMasterRequest()) {
+        if (!cache->doMasterRequest()) {
             //This can happen if I am the owner of a block and see an upgrade
             //while the block was in my WB Buffers.  I just remove the
             //wb and de-assert the masterRequest
@@ -243,7 +243,7 @@ BaseCache::CacheEvent::process()
         else if (!cachePort->isCpuSide)
         {            //MSHR
             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
-            if (cachePort->cache->doMasterRequest()) {
+            if (!cachePort->cache->doMasterRequest()) {
                 //This can happen if I am the owner of a block and see an upgrade
                 //while the block was in my WB Buffers.  I just remove the
                 //wb and de-assert the masterRequest