From: Kenneth Graunke Date: Fri, 8 Mar 2019 04:14:59 +0000 (-0800) Subject: iris: Fix TES gl_PatchVerticesIn handling. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04ff2e3fbbb981606aa4d469316f6f00cc8083db;p=mesa.git iris: Fix TES gl_PatchVerticesIn handling. 1. If we switch the TCS for one with a different number of output vertices, then the TES's gl_PatchVerticesIn value will change. We need to re-upload in this case. For now, re-emit constants whenever the TCS/TES are swapped out. 2. If there is no TCS, then we can't grab gl_PatchVerticesIn from the TCS info. Since it's a passthrough, we can just use the primitive's patch count (like the TCS gl_PatchVerticesIn does). Fixes KHR-GL45.tessellation_shader.single.max_patch_vertices and KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn. Reviewed-by: Caio Marcelo de Oliveira Filho --- diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 279dbc3a943..6dc3289f6cd 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -912,6 +912,13 @@ iris_update_compiled_tes(struct iris_context *ice) IRIS_DIRTY_BINDINGS_TES | IRIS_DIRTY_CONSTANTS_TES; } + + /* TODO: Could compare and avoid flagging this. */ + const struct shader_info *tes_info = &ish->nir->info; + if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) { + ice->state.dirty |= IRIS_DIRTY_CONSTANTS_TES; + ice->state.shaders[MESA_SHADER_TESS_EVAL].cbuf0_needs_upload = true; + } } /** diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 427419acfb9..d00186d6657 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -2490,9 +2490,10 @@ upload_uniforms(struct iris_context *ice, assert(stage == MESA_SHADER_TESS_EVAL); const struct shader_info *tcs_info = iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL); - assert(tcs_info); - - value = tcs_info->tess.tcs_vertices_out; + if (tcs_info) + value = tcs_info->tess.tcs_vertices_out; + else + value = ice->state.vertices_per_patch; } } else if (sysval >= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X && sysval <= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W) {