From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 29 Nov 2018 07:10:10 +0000 (+0000)
Subject: on branch, obtain the predicate inversion flag
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05028179960b97a80aa01d0217c0955007024eb5;p=riscv-isa-sim.git

on branch, obtain the predicate inversion flag
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 4389fd6..a4ebbc4 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -66,6 +66,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #ifdef INSN_TYPE_BRANCH
   reg_t target_pred = ~0x0;
   bool zeroingtarg = false;
+  bool invtarg = false;
 #endif
   sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen,
                  INSN_SRC_FLEN, INSN_DEST_FLEN,
@@ -109,9 +110,9 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
       _target_reg = r->regidx;
       target_reg = &_target_reg;
 #ifdef INSN_TYPE_C_BRANCH
-      insn.predicate(0, true, zeroingtarg);
+      target_pred = insn.predicate(0, true, zeroingtarg, invtarg);
 #else
-      insn.predicate(s_insn.rs2(), true, zeroingtarg);
+      target_pred = insn.predicate(s_insn.rs2(), true, zeroingtarg, invtarg);
 #endif
       fprintf(stderr, "branch pred reg %ld pred %lx\n",
                        _target_reg, target_pred);