From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 5 Nov 2021 09:08:50 +0000 (+0100)
Subject: Add missing changelog item
X-Git-Tag: yosys-0.11~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=051b234df66c242c7a81b0f37d53c0637649ddd1;p=yosys.git

Add missing changelog item
---

diff --git a/CHANGELOG b/CHANGELOG
index 6feea4162..e35159123 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -21,6 +21,7 @@ Yosys 0.10 .. Yosys 0.10-dev
     - Importer support for PRIM_BUFIF1
     - Option to use Verific without VHDL support
     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+    - Added -cfg option for getting/setting Verific runtime flags
 
 Yosys 0.9 .. Yosys 0.10
 --------------------------