From: Sofiane Naci Date: Tue, 2 Apr 2013 09:02:17 +0000 (+0000) Subject: aarch64.md (*mov_aarch64): Add alternatives for scalar move. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=051d0e2f45082269e127c6e048c69faee664b129;p=gcc.git aarch64.md (*mov_aarch64): Add alternatives for scalar move. * config/aarch64/aarch64.md (*mov_aarch64): Add alternatives for scalar move. * config/aarch64/aarch64.c (aarch64_simd_scalar_immediate_valid_for_move): New. * config/aarch64/aarch64-protos.h (aarch64_simd_scalar_immediate_valid_for_move): New. * config/aarch64/constraints.md (Dh, Dq): New. * config/aarch64/iterators.md (hq): New. From-SVN: r197341 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f1064e6aa61..1bf033d2aa4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2013-04-02 Sofiane Naci + + * config/aarch64/aarch64.md (*mov_aarch64): Add alternatives for + scalar move. + * config/aarch64/aarch64.c + (aarch64_simd_scalar_immediate_valid_for_move): New. + * config/aarch64/aarch64-protos.h + (aarch64_simd_scalar_immediate_valid_for_move): New. + * config/aarch64/constraints.md (Dh, Dq): New. + * config/aarch64/iterators.md (hq): New. + 2013-04-02 Eric Botcazou * reorg.c (get_branch_condition): Deal with conditional returns. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 5d0072f9da7..7ebbf51a201 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -151,6 +151,7 @@ bool aarch64_regno_ok_for_base_p (int, bool); bool aarch64_regno_ok_for_index_p (int, bool); bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode); bool aarch64_simd_imm_zero_p (rtx, enum machine_mode); +bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode); bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool); bool aarch64_symbolic_address_p (rtx); bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 6a024d09044..bd33cd66b8d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6407,6 +6407,21 @@ aarch64_simd_gen_const_vector_dup (enum machine_mode mode, int val) return gen_rtx_CONST_VECTOR (mode, v); } +/* Check OP is a legal scalar immediate for the MOVI instruction. */ + +bool +aarch64_simd_scalar_immediate_valid_for_move (rtx op, enum machine_mode mode) +{ + enum machine_mode vmode; + + gcc_assert (!VECTOR_MODE_P (mode)); + vmode = aarch64_preferred_simd_mode (mode); + rtx op_v = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (op)); + int retval = aarch64_simd_immediate_valid_for_move (op_v, vmode, 0, + NULL, NULL, NULL, NULL); + return retval; +} + /* Construct and return a PARALLEL RTX vector. */ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ab73ae3c673..01f04aade43 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -763,19 +763,21 @@ ) (define_insn "*mov_aarch64" - [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r,r,m, r,*w") - (match_operand:SHORT 1 "general_operand" " r,M,m,rZ,*w,r"))] + [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, *w,r, m, r,*w,*w") + (match_operand:SHORT 1 "general_operand" " r,M,D,m,rZ,*w, r,*w"))] "(register_operand (operands[0], mode) || aarch64_reg_or_zero (operands[1], mode))" "@ mov\\t%w0, %w1 mov\\t%w0, %1 + movi\\t%0., %1 ldr\\t%w0, %1 str\\t%w1, %0 umov\\t%w0, %1.[0] - dup\\t%0., %w1" - [(set_attr "v8type" "move,alu,load1,store1,*,*") - (set_attr "simd_type" "*,*,*,*,simd_movgp,simd_dupgp") + dup\\t%0., %w1 + dup\\t%0, %1.[0]" + [(set_attr "v8type" "move,alu,alu,load1,store1,*,*,*") + (set_attr "simd_type" "*,*,simd_move_imm,*,*,simd_movgp,simd_dupgp,simd_dup") (set_attr "mode" "") (set_attr "simd_mode" "")] ) diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 917b93922cd..18ac16a3160 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -152,6 +152,22 @@ NULL, NULL, NULL, NULL, NULL) != 0"))) +(define_constraint "Dh" + "@internal + A constraint that matches an immediate operand valid for\ + AdvSIMD scalar move in HImode." + (and (match_code "const_int") + (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, + HImode)"))) + +(define_constraint "Dq" + "@internal + A constraint that matches an immediate operand valid for\ + AdvSIMD scalar move in QImode." + (and (match_code "const_int") + (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, + QImode)"))) + (define_constraint "Dl" "@internal A constraint that matches vector of immediates for left shifts." diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index ce81ac5ce87..863a4af0346 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -249,6 +249,9 @@ ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) +;; For constraints used in scalar immediate vector moves +(define_mode_attr hq [(HI "h") (QI "q")]) + ;; For scalar usage of vector/FP registers (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") (V8QI "") (V16QI "")