From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 23:05:41 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~283
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=052060f10906ca859d2313b86800e110bd34b79f;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

052060f10906ca859d2313b86800e110bd34b79f
diff --cc backends/aiger/xaiger.cc
index 632a5c8d5,69f63486c..a1085addf
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@@ -250,17 -240,7 +256,17 @@@ struct XAigerWrite
  
  			log_assert(!holes_mode);
  
 +			if (cell->type == "$__ABC_FF_")
 +			{
 +				SigBit D = sigmap(cell->getPort("\\D").as_bit());
 +				SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
 +				unused_bits.erase(D);
 +				undriven_bits.erase(Q);
 +				alias_map[Q] = D;
 +				continue;
 +			}
 +
- 			RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
+ 			RTLIL::Module* inst_module = module->design->module(cell->type);
  			if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
  				abc_box_seen = true;
  
diff --cc techlibs/xilinx/Makefile.inc
index 860fcd88c,17c5df37d..c9a3a49fb
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@@ -30,8 -30,8 +30,9 @@@ $(eval $(call add_share_file,share/xili
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
  
 +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
diff --cc techlibs/xilinx/abc_xc7.box
index 633e2d484,3789ff350..69ff9aeab
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@@ -48,26 -53,6 +53,26 @@@ RAM64X1D 6 0 15 
  # SLICEM/A6LUT + F7[AB]MUX
  # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  # Outputs: DPO SPO
- RAM128X1D 6 0 17 2
+ RAM128X1D 7 0 17 2
  -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
  1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 +
 +# Inputs: C CE D R \$pastQ
 +# Outputs: Q
 +FDRE 7 1 5 1
 +- 109 -46 358 0
 +
 +# Inputs: C CE D S \$pastQ
 +# Outputs: Q
 +FDSE 8 0 5 1
 +- 109 -46 358 0
 +
 +# Inputs: C CE CLR D \$pastQ
 +# Outputs: Q
 +FDCE 9 0 5 1
 +- 109 - -46 0
 +
 +# Inputs: C CE D PRE \$pastQ
 +# Outputs: Q
 +FDPE 10 0 5 1
 +- 109 -46 - 0
diff --cc techlibs/xilinx/synth_xilinx.cc
index cdc64db1d,77daa745c..2455c2885
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -299,11 -372,10 +372,11 @@@ struct SynthXilinxPass : public ScriptP
  			else if (abc9) {
  				if (family != "xc7")
  					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 +				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
  				if (nowidelut)
- 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+ 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
  				else
- 					run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+ 					run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
  			}
  			else {
  				if (nowidelut)