From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 25 Jul 2014 10:49:51 +0000 (+0200)
Subject: Fixed memory corruption in "opt_reduce" pass
X-Git-Tag: yosys-0.4~434
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0520bfea892291a131134411d587034fcd36bf1c;p=yosys.git

Fixed memory corruption in "opt_reduce" pass
---

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 913855f48..0cc16ee67 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -312,12 +312,14 @@ struct OptReduceWorker
 
 			// merge identical inputs on $mux and $pmux cells
 
-			for (auto &cell_it : module->cells)
-			{
-				RTLIL::Cell *cell = cell_it.second;
-				if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || !design->selected(module, cell))
-					continue;
+			std::vector<RTLIL::Cell*> cells;
 
+			for (auto &it : module->cells)
+				if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
+					cells.push_back(it.second);
+
+			for (auto cell : cells)
+			{
 				// this optimization is to aggressive for most coarse-grain applications.
 				// but we always want it for multiplexers driving write enable ports.
 				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y"))))