From: lkcl Date: Tue, 11 Aug 2020 12:33:51 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~2285 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05233f0647d0959065eb0c8297da1c9fb41d84c0;p=libreriscv.git --- diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn index 0988b42e2..483ea4b49 100644 --- a/3d_gpu/architecture/regfile.mdwn +++ b/3d_gpu/architecture/regfile.mdwn @@ -4,13 +4,14 @@ Discussion: * -A minimum of 4 register files are required for POWER: +These register files are required for POWER: * Floating-point * Integer * Control and Condition Code Registers (CR0-7) * SPRs (Special Purpose Registers) -* Fast Registers (PC, MSR, CTR, LR, SRR0, SRR1 etc.) +* Fast Registers (CTR, LR, SRR0, SRR1 etc.) +* "State" Registers (CIA, MSR, SimpleV VL) Source code: @@ -28,14 +29,16 @@ For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit. - CA(32) - 2-bit - OV(32) - 2-bit - SO - 1 bit -* FAST regfile: 7x 64-bit, full 3R2W (possibly greater) - - MSR: 64-bit - - PC: 64-bit +* FAST regfile: 5x 64-bit, full 3R2W (possibly greater) - LR: 64-bit - CTR: 64-bit - TAR: 64-bit - SRR1: 64-bit - SRR2: 64-bit +* STATE regfile: 3x 64-bit, 2R1W (possibly greater) + - MSR: 64-bit + - PC: 64-bit + - SVSTATE: 64-bit # Connectivity between regfiles and Function Units