From: lkcl <lkcl@web>
Date: Thu, 16 Sep 2021 08:54:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~110
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=053ad14e053f2053fbb6f68df33c4ea7e8ff2670;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 21c809fdf..4e5998ec2 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Normal Mode for SVP64
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=574>
@@ -5,13 +7,13 @@
 * [[svp64]]
 
 Normal SVP64 Mode covers Arithmetic and Logical operations
-to provide suitable additional behaviour.
+to provide suitable additional behaviour.  The Mode
+field is bits 19-23 of the [[svp64]] RM Field.
 
 Table of contents:
 
 [[!toc]]
 
-
 # Mode
 
 Mode is an augmentation of SV behaviour, providing additional