From: Florent Kermarrec Date: Fri, 8 May 2020 11:17:59 +0000 (+0200) Subject: cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use... X-Git-Tag: 24jan2021_ls180~370 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05869beb722e6862118d5879fde57e90a8dc04e2;p=litex.git cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :)) --- diff --git a/litex/soc/cores/led.py b/litex/soc/cores/led.py new file mode 100644 index 00000000..727000e0 --- /dev/null +++ b/litex/soc/cores/led.py @@ -0,0 +1,35 @@ +# This file is Copyright (c) 2020 Florent Kermarrec +# License: BSD + +from migen import * +from migen.genlib.misc import WaitTimer + +from litex.soc.interconnect.csr import * + +# Led Chaser --------------------------------------------------------------------------------------- + +class LedChaser(Module, AutoCSR): + def __init__(self, pads, sys_clk_freq, period=1e0): + self.control = CSRStorage(fields=[ + CSRField("mode", size=2, values=[ + ("``0b0``", "Chaser mode."), + ("``0b1``", "CPU mode."), + ]) + ]) + self.value = CSRStorage(len(pads), description="Control value when in CPU mode.") + + # # # + + n = len(pads) + chaser = Signal(n) + timer = WaitTimer(int(period*sys_clk_freq/(2*n))) + self.submodules += timer + self.comb += timer.wait.eq(~timer.done) + self.sync += If(timer.done, chaser.eq(Cat(~chaser[-1], chaser))) + self.comb += [ + If(self.control.fields.mode, + pads.eq(self.value.storage) + ).Else( + pads.eq(chaser) + ) + ]