From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Apr 2019 02:33:57 +0000 (+0100)
Subject: replace switch statement with straight index to array
X-Git-Tag: div_pipeline~2193
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0589741a42b758446c479599a5e43962630189c4;p=soc.git

replace switch statement with straight index to array
---

diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index cdf88295..1bc1e97d 100644
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -169,15 +169,12 @@ class SetAssociativeCache():
         ]
 
         with m.If(self.encoder.single_match):
-            with m.Switch(self.encoder.o):
-                for i in range(len(self.write_array)):
-                    with m.Case(i):
-                        write_port = self.write_array[i]
-                        m.d.comb += [
-                            write_port.en.eq(1),
-                            write_port.addr.eq(self.cset),
-                            write_port.data.eq(Cat(1, self.data_i, self.tag))
-                        ]
+            write_port = self.write_array[self.encoder.o]
+            m.d.comb += [
+                write_port.en.eq(1),
+                write_port.addr.eq(self.cset),
+                write_port.data.eq(Cat(1, self.data_i, self.tag))
+            ]
 
     def write(self, m):
         with m.FSM() as fsm_write:
@@ -219,4 +216,4 @@ if __name__ == '__main__':
     sac = SetAssociativeCache(4, 4, 4, 4)
     vl = rtlil.convert(sac)
     with open("SetAssociativeCache.il", "w") as f:
-        f.write(vl)
\ No newline at end of file
+        f.write(vl)