From: Luke Kenneth Casson Leighton Date: Tue, 29 Jun 2021 15:22:17 +0000 (+0100) Subject: re-enable accidentally-disabled sv ld/st tests X-Git-Tag: xlen-bcd~356 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=059803f282dea0abbc1ae947e4355205368aca45;p=openpower-isa.git re-enable accidentally-disabled sv ld/st tests --- diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py index 99e4f517..64755d58 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py @@ -22,7 +22,7 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) - def tst_sv_load_store_elementstride(self): + def test_sv_load_store_elementstride(self): """>>> lst = ["addi 1, 0, 0x0010", "addi 2, 0, 0x0008", "addi 5, 0, 0x1234", @@ -67,7 +67,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64)) self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64)) - def tst_sv_load_store_unitstride(self): + def test_sv_load_store_unitstride(self): """>>> lst = ["addi 1, 0, 0x0010", "addi 2, 0, 0x0008", "addi 5, 0, 0x1234",