From: lkcl <lkcl@web>
Date: Wed, 15 Sep 2021 12:16:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05a2bc8dfc96a97c1187be2f8c8a380c931c9a43;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 2853af438..c8c177a3b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -186,7 +186,8 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 
 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 
-These are the modes for everything except [[sv/ldst]] and [[sv/branches]]:
+These are the modes for everything except [[sv/ldst]],
+[[sv/cr_ops]] and [[sv/branches]] which are covered separately:
 
 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.