From: Clifford Wolf Date: Thu, 9 May 2019 13:31:40 +0000 (+0200) Subject: Add $stop to documentation X-Git-Tag: yosys-0.9~132 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d;p=yosys.git Add $stop to documentation Signed-off-by: Clifford Wolf --- diff --git a/README.md b/README.md index 195329a37..efb74ef4e 100644 --- a/README.md +++ b/README.md @@ -416,9 +416,10 @@ Verilog Attributes and non-standard features expressions as . If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` -- The system tasks ``$finish`` and ``$display`` are supported in initial blocks - in an unconditional context (only if/case statements on parameters - and constant values). The intended use for this is synthesis-time DRC. +- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in + initial blocks in an unconditional context (only if/case statements on + expressions over parameters and constant values are allowed). The intended + use for this is synthesis-time DRC. - There is limited support for converting specify .. endspecify statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in