From: kajoljain379 Date: Wed, 20 Feb 2019 05:58:03 +0000 (+0530) Subject: arch-power: Add support for timebase updates X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05a513e80f70f1c203b0a1a89b2b0852c410c59c;p=gem5.git arch-power: Add support for timebase updates * Added support to update INTREG_TB on checkInterrupt * Initialize TB register * Add support for decrementer interrupt to check for ee bit to handle nested interrupt. Change-Id: I2e1f37871879bb9370eba17ddb5d23562665b138 Signed-off-by: kajoljain379 --- diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh index 40f5c3fce..d4bfd876e 100644 --- a/src/arch/power/interrupts.hh +++ b/src/arch/power/interrupts.hh @@ -88,11 +88,15 @@ class Interrupts : public SimObject checkInterrupts(ThreadContext *tc) { //panic("Interrupts::checkInterrupts not implemented.\n"); - if ( tc->readIntReg(INTREG_DEC) == 0) { + Msr msr = tc->readIntReg(INTREG_MSR); + tc->setIntReg(INTREG_TB , tc->readIntReg(INTREG_TB)+1); + if ( tc->readIntReg(INTREG_DEC) == 0 && msr.ee) { si = true; return true; } - else { + else if (tc->readIntReg(INTREG_DEC) == 0 && !msr.ee) { + return false; + } else { tc->setIntReg(INTREG_DEC , tc->readIntReg(INTREG_DEC)-1); return false; } diff --git a/src/arch/power/system.cc b/src/arch/power/system.cc index 389bc625b..1df07a506 100644 --- a/src/arch/power/system.cc +++ b/src/arch/power/system.cc @@ -73,11 +73,11 @@ PowerSystem::initState() Msr msr = 0x9000000000000001; tc->setIntReg(INTREG_DEC , 0xffffffffffffffff); // This PVR is specific to power9 + // Setting TB register to 0 + tc->setIntReg(INTREG_TB , 0x0); tc->setIntReg(INTREG_PVR , 0x004e1100); tc->setIntReg(INTREG_MSR , msr); //ArgumentReg0 is initialized with 0xc00000 because in linux/system.cc //dtb is loaded at 0xc00000 tc->setIntReg(ArgumentReg0, 0x1800000); - /* Perform a system reset */ - tc->pcState(0x100); }