From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Nov 2018 05:40:55 +0000 (+0000)
Subject: add reg csr hyperlink
X-Git-Tag: convert-csv-opcode-to-binary~4847
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05bf429ab5b569ba14d45d6a9ed85df61b71f73a;p=libreriscv.git

add reg csr hyperlink
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 1b7f676ea..063049791 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -807,7 +807,7 @@ It is **purely** about compacting what would otherwise be contiguous
 instructions that use sequentially-increasing register numbers down
 to the **one** instruction.
 
-# Instructions
+# Instructions <a name="instructions" />
 
 Despite being a 98% complete and accurate topological remap of RVV
 concepts and functionality, no new instructions are needed.