From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 22:31:32 +0000 (-0800)
Subject: read_aiger: $lut prefix in front
X-Git-Tag: working-ls180~864^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05c8858a907f0f188f1687ede260c2e1a97efe38;p=yosys.git

read_aiger: $lut prefix in front
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f6b2a639d..a4b1e6fec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1001,9 +1001,9 @@ void AigerReader::post_process()
 		if (cell->type != "$lut") continue;
 		auto y_port = cell->getPort("\\Y").as_bit();
 		if (y_port.wire->width == 1)
-			module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
+			module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
 		else
-			module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
+			module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
 	}
 }