From: Gabe Black Date: Wed, 2 Jun 2010 17:58:04 +0000 (-0500) Subject: ARM: Restrict the shift amount from a register to 8 bits. X-Git-Tag: stable_2012_02_02~1312 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05d880f7a1326f83076614442bc38c5332624dd4;p=gem5.git ARM: Restrict the shift amount from a register to 8 bits. The shift amount when taken from a register is supposed to be truncated to an 8 bit value. --- diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index f96416168..daac4ed3c 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -96,7 +96,7 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" def buildDataInst(mnem, code, flagType = "logic"): global header_output, decoder_output, exec_output