From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 27 Jan 2019 07:23:44 +0000 (+0100)
Subject: soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
X-Git-Tag: 24jan2021_ls180~1401
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05dcb5cadce88c05e2020a293ea5273396702eb9;p=litex.git

soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
---

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 7e8b78d7..942e4b7d 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -140,7 +140,7 @@ class Timeout(Module):
 
         # # #
 
-        timer = WaitTimer(cycles)
+        timer = WaitTimer(int(cycles))
         self.submodules += timer
         self.comb += [
             timer.wait.eq(master.stb & master.cyc & ~master.ack),
@@ -153,7 +153,7 @@ class Timeout(Module):
 
 
 class InterconnectShared(Module):
-    def __init__(self, masters, slaves, register=False, timeout_cycles=2**16):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         shared = Interface()
         self.submodules.arbiter = Arbiter(masters, shared)
         self.submodules.decoder = Decoder(shared, slaves, register)