From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 Mar 2019 02:17:52 +0000 (+0000)
Subject: add AXI4 migen
X-Git-Tag: convert-csv-opcode-to-binary~4727
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05efe9afc7dddd90f6b86829a4c0bf065f01b543;p=libreriscv.git

add AXI4 migen
---

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index c2be19648..61beb10e3 100644
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -4,4 +4,8 @@ See also [[wishbone]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
-* https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl
+* <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
+
+# AXI4 in nmigen
+
+* <https://github.com/peteut/migen-axi>