From: Gabe Black Date: Sun, 1 Nov 2020 11:52:41 +0000 (-0800) Subject: sparc: Convert SPARC to use local register index storage. X-Git-Tag: develop-gem5-snapshot~421 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05f4da760045a6d687aa8a9bdf579fffc6710b7d;p=gem5.git sparc: Convert SPARC to use local register index storage. Once all ISAs are converted, the base StaticInst class will be able to drop its local arrays, and will no longer need to know what the global maximum number of source or destination registers is for a given instruction. Most of the convertion was very simple and just involved adding tags to declare and install the register arrays in all the class definitions. Since SPARC has a relatively simple ISA definition, there weren't many places that needed to be updated. The exception was the BlockMem template, which was declaring the microop classes within the body of the macroop. That was ok when those declarations didn't need anything other than the name of their parent, but now they also need to know how big to declare their arrays based on their actual implementation. To facilitate that, and to significantly streamline the definition of the macroop class, the microop class definitions were moved to their own template, and only the declaration was left in the parent class. Change-Id: I09e6b1d1041c6a0aeaee63ce5f9a18cf482b6203 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36879 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 9ab7699ec..8a3f1746a 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -31,6 +31,9 @@ def template BasicDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor. %(class_name)s(ExtMachInst machInst); @@ -45,6 +48,9 @@ def template FpBasicDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor. %(class_name)s(ExtMachInst machInst); @@ -60,6 +66,9 @@ def template BasicDeclareWithMnemonic {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor. %(class_name)s(const char *mnemonic, ExtMachInst machInst); @@ -72,6 +81,7 @@ def template BasicConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -81,6 +91,7 @@ def template BasicConstructorWithMnemonic {{ %(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst) : %(base_class)s(mnemonic, machInst, %(op_class)s) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index 2850d3285..03544787f 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -37,6 +37,9 @@ def template MemDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index b79eb3f79..fb9cfc470 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -30,120 +30,43 @@ // def template BlockMemDeclare {{ - /** - * Static instruction class for a block memory operation - */ - class %(class_name)s : public %(base_class)s - { - public: - // Constructor - %(class_name)s(ExtMachInst machInst); - - protected: - class %(class_name)s_0 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_0(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - - class %(class_name)s_1 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_1(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - - class %(class_name)s_2 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_2(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - - class %(class_name)s_3 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_3(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - - class %(class_name)s_4 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_4(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - - class %(class_name)s_5 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_5(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; + /** + * Static instruction class for a block memory operation + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor + %(class_name)s(ExtMachInst machInst); + + protected: + class %(class_name)s_0; + class %(class_name)s_1; + class %(class_name)s_2; + class %(class_name)s_3; + class %(class_name)s_4; + class %(class_name)s_5; + class %(class_name)s_6; + class %(class_name)s_7; + }; +}}; - class %(class_name)s_6 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_6(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; +def template BlockMemMicroDeclare {{ + class %(class_name)s::%(class_name)s_%(micro_pc)s : + public %(base_class)sMicro + { + private: + %(reg_idx_arr_decl)s; + + public: + // Constructor + %(class_name)s_%(micro_pc)s(ExtMachInst machInst); + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; + }; - class %(class_name)s_7 : public %(base_class)sMicro - { - public: - // Constructor - %(class_name)s_7(ExtMachInst machInst); - Fault execute(ExecContext *, - Trace::InstRecord *) const override; - Fault initiateAcc(ExecContext *, - Trace::InstRecord *) const override; - Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const override; - }; - }; }}; // Basic instruction class constructor template. @@ -170,6 +93,7 @@ def template BlockMemMicroConstructor {{ %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", machInst, %(op_class)s, %(micro_pc)s * 8) { + %(set_reg_idx_arr)s; %(constructor)s; %(set_flags)s; } @@ -184,9 +108,12 @@ let {{ addrCalcReg = 'EA = Rs1 + Rs2 + offset;' addrCalcImm = 'EA = Rs1 + imm + offset;' iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) - iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) - header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) - decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) + iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', + code, opt_flags) + header_output = BlockMemDeclare.subst(iop) + \ + BlockMemDeclare.subst(iop_imm) + decoder_output = BlockMemConstructor.subst(iop) + \ + BlockMemConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) matcher = re.compile(r'Frd_N') exec_output = '' @@ -195,7 +122,8 @@ let {{ if (microPc == 7): flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" + flag_code = "flags[IsDelayedCommit] = true; " \ + "flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) @@ -209,6 +137,8 @@ let {{ "fault_check": faultCode, "micro_pc": microPc, "set_flags": flag_code, "EA_trunc" : TruncateEA}, opt_flags) + header_output += BlockMemMicroDeclare.subst(iop) + header_output += BlockMemMicroDeclare.subst(iop_imm) decoder_output += BlockMemMicroConstructor.subst(iop) decoder_output += BlockMemMicroConstructor.subst(iop_imm) exec_output += doDualSplitExecute( diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa index 4a4451314..82f5692c0 100644 --- a/src/arch/sparc/isa/formats/nop.isa +++ b/src/arch/sparc/isa/formats/nop.isa @@ -34,6 +34,9 @@ def template NopDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst); }; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 7530cdfe2..a0c3a18d4 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -33,6 +33,7 @@ def template ControlRegConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, "%(reg_name)s") { + %(set_reg_idx_arr)s; %(constructor)s; } }};