From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sat, 27 Aug 2016 02:53:25 +0000 (-0700)
Subject: Update to new breakpoint & counter spec
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=05f70dc4925262713355bba0cedfd3f5c0d485e5;p=riscv-tests.git

Update to new breakpoint & counter spec
---

diff --git a/env b/env
index 52947c5..ce70afb 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 52947c5489f868174e9251a98376274183e35b40
+Subproject commit ce70afbf50a203be04bc326326cfa75831fe7f5d
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index b975331..b318c30 100644
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -16,24 +16,23 @@ RVTEST_CODE_BEGIN
   # Set up breakpoint to trap on M-mode fetches.
   li TESTNUM, 2
 
-  # Skip tdrselect if hard-wired.
-  li a0, 1<<(_RISCV_SZLONG-1)
-  csrw tdrselect, a0
-  csrr a1, tdrselect
-  bne a0, a1, pass
+  # Skip tselect if hard-wired.
+  csrw tselect, x0
+  csrr a1, tselect
+  bne x0, a1, pass
 
   # Make sure there's a breakpoint there.
-  csrr a0, tdrdata1
+  csrr a0, tdata1
   srli a0, a0, _RISCV_SZLONG-4
-  li a1, 1
+  li a1, 2
   bne a0, a1, pass
 
   la a2, 1f
-  csrw tdrdata2, a2
-  li a0, BPCONTROL_M | BPCONTROL_X
-  csrw tdrdata1, a0
+  csrw tdata2, a2
+  li a0, MCONTROL_M | MCONTROL_EXECUTE
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr a1, tdrdata1
+  csrr a1, tdata1
   andi a1, a1, 0x7ff
   bne a0, a1, 2f
   .align 2
@@ -48,14 +47,14 @@ RVTEST_CODE_BEGIN
 2:
   # Set up breakpoint to trap on M-mode reads.
   li TESTNUM, 4
-  li a0, BPCONTROL_M | BPCONTROL_R
-  csrw tdrdata1, a0
+  li a0, MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr a1, tdrdata1
+  csrr a1, tdata1
   andi a1, a1, 0x7ff
   bne a0, a1, 2f
   la a2, data1
-  csrw tdrdata2, a2
+  csrw tdata2, a2
 
   # Trap handler should skip this instruction.
   lw a2, (a2)
@@ -68,10 +67,10 @@ RVTEST_CODE_BEGIN
 2:
   # Set up breakpoint to trap on M-mode stores.
   li TESTNUM, 6
-  li a0, BPCONTROL_M | BPCONTROL_W
-  csrw tdrdata1, a0
+  li a0, MCONTROL_M | MCONTROL_STORE
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr a1, tdrdata1
+  csrr a1, tdata1
   andi a1, a1, 0x7ff
   bne a0, a1, 2f
 
@@ -84,21 +83,21 @@ RVTEST_CODE_BEGIN
   bnez a2, fail
 
   # Try to set up a second breakpoint.
-  li a0, (1<<(_RISCV_SZLONG-1)) + 1
-  csrw tdrselect, a0
-  csrr a1, tdrselect
+  li a0, 1
+  csrw tselect, a0
+  csrr a1, tselect
   bne a0, a1, pass
 
   # Make sure there's a breakpoint there.
-  csrr a0, tdrdata1
+  csrr a0, tdata1
   srli a0, a0, _RISCV_SZLONG-4
-  li a1, 1
+  li a1, 2
   bne a0, a1, pass
 
-  li a0, BPCONTROL_M | BPCONTROL_R
-  csrw tdrdata1, a0
+  li a0, MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
   la a3, data2
-  csrw tdrdata2, a3
+  csrw tdata2, a3
 
   # Make sure the second breakpoint triggers.
   li TESTNUM, 8
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 68f6fb1..1f7bb77 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -42,12 +42,6 @@ RVTEST_CODE_BEGIN
   beqz a0, finish # if no user mode, skip the rest of these checks
 #endif
 
-  # Make sure writing the cycle counter causes an exception.
-  # Don't run in supervisor, as we don't delegate illegal instruction traps.
-#ifdef __MACHINE_MODE
-  TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
-#endif
-
   # jump to user land
   li t0, SSTATUS_SPP
   csrc sstatus, t0
@@ -56,6 +50,12 @@ RVTEST_CODE_BEGIN
   sret
   1:
 
+  # Make sure writing the cycle counter causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+#endif
+
   # Make sure reading status in user mode causes an exception.
   # Don't run in supervisor, as we don't delegate illegal instruction traps.
 #ifdef __MACHINE_MODE