From: Michel Dänzer <michel@tungstengraphics.com>
Date: Wed, 28 Feb 2007 16:46:07 +0000 (+0100)
Subject: i915tex: Sync pages differently when crossing pipe borders.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0609b6afa8117893d7b36468158ac6ec2f5642bc;p=mesa.git

i915tex: Sync pages differently when crossing pipe borders.

Don't flip (up to twice) immediately but just arrange things such that the
pages will be in sync on both pipes on the next flip.
---

diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 5eb2a8e5d09..9f1b25ef380 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -253,19 +253,25 @@ intelWindowMoved(struct intel_context *intel)
 			 pf_active ? "" : "in");
 
       if (pf_active) {
-	 int i;
-
 	 /* Sync pages between pipes if we're flipping on both at the same time */
-	 for (i = 0; i < 2 && pf_pipes != intel_fb->pf_pipes &&
-		intel_fb->pf_pipes == 0x3 &&
-		(intel->sarea->pf_current_page & 0x3) !=
-		((intel->sarea->pf_current_page) >> 2 & 0x3); i++) {
-	    drm_i915_flip_t flip;
-
-	    flip.pipes = (intel_fb->pf_current_page ==
-			  (intel->sarea->pf_current_page & 0x3)) ? 0x2 : 0x1;
-
-	    drmCommandWrite(intel->driFd, DRM_I915_FLIP, &flip, sizeof(flip));
+	 if (pf_pipes == 0x3 &&	pf_pipes != intel_fb->pf_pipes &&
+	     (intel->sarea->pf_current_page & 0x3) !=
+	     (((intel->sarea->pf_current_page) >> 2) & 0x3)) {
+	    if (intel_fb->pf_current_page ==
+		(intel->sarea->pf_current_page & 0x3)) {
+	       /* XXX: This is ugly, but emitting two flips 'in a row' can cause
+		* lockups for unknown reasons.
+		*/
+               intel->sarea->pf_current_page =
+		  intel->sarea->pf_current_page & 0x3;
+	       intel->sarea->pf_current_page |=
+		  intel->sarea->pf_current_page << 2;
+	    } else {
+               intel->sarea->pf_current_page =
+		  intel->sarea->pf_current_page & (0x3 << 2);
+	       intel->sarea->pf_current_page |=
+		  intel->sarea->pf_current_page >> 2;
+	    }
 	 }
 
 	 intel_fb->pf_pipes = pf_pipes;