From: whitequark Date: Wed, 22 Jul 2020 12:14:39 +0000 (+0000) Subject: wip (#439) X-Git-Tag: 24jan2021_ls180 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=060ad2584edccad62e59ddd209f593a4dfc4670a;p=nmigen.git wip (#439) --- diff --git a/nmigen/sim/cxxsim.py b/nmigen/sim/cxxsim.py index a637c85..5edce5d 100644 --- a/nmigen/sim/cxxsim.py +++ b/nmigen/sim/cxxsim.py @@ -116,13 +116,13 @@ class Simulator(SimulatorCore): process.reset() def _real_step(self): - for process in self._processes: - if process.runnable: - process.runnable = False - process.run() - while True: self._state.eval() + for process in self._processes: + if process.runnable: + process.runnable = False + process.run() + if not self._state.commit(): break