From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 09:36:32 +0000 (+0000)
Subject: opt_lut: use a worklist, and revisit cells affected by elimination.
X-Git-Tag: yosys-0.9~349^2~1^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06143ab33f4064677586be2a2b0d763f0818e856;p=yosys.git

opt_lut: use a worklist, and revisit cells affected by elimination.
---

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 8c564b0ed..a79a9a2da 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -189,7 +189,8 @@ struct OptLutWorker
 
 		log("\n");
 		log("Eliminating LUTs.\n");
-		for (auto lut : luts)
+		pool<RTLIL::Cell*> worklist = luts;
+		while (worklist.size())
 		{
 			if (limit == 0)
 			{
@@ -197,6 +198,7 @@ struct OptLutWorker
 				break;
 			}
 
+			auto lut = worklist.pop();
 			SigSpec lut_input = sigmap(lut->getPort("\\A"));
 			pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
 
@@ -262,8 +264,13 @@ struct OptLutWorker
 				else
 				{
 					SigSpec lut_output = lut->getPort("\\Y");
-					module->connect(lut_output, value);
+					for (auto &port : index.query_ports(lut_output))
+					{
+						if (port.cell != lut && luts.count(port.cell))
+							worklist.insert(port.cell);
+					}
 
+					module->connect(lut_output, value);
 					module->remove(lut);
 					luts.erase(lut);
 					luts_arity.erase(lut);
@@ -280,7 +287,7 @@ struct OptLutWorker
 
 		log("\n");
 		log("Combining LUTs.\n");
-		pool<RTLIL::Cell*> worklist = luts;
+		worklist = luts;
 		while (worklist.size())
 		{
 			if (limit == 0)