From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 04:35:03 +0000 (+0100)
Subject: add rv_div (signed and unsigned) to replace operator /
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0617dfb0b8ea433bc7c4f824ef4f082216741b6a;p=riscv-isa-sim.git

add rv_div (signed and unsigned) to replace operator /
---

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 9cbe8d6..b4dd9f2 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -6,4 +6,4 @@ if(rhs == 0)
 else if(lhs == INT64_MIN && rhs == -1)
   WRITE_RD(lhs);
 else
-  WRITE_RD(sext_xlen(lhs / rhs));
+  WRITE_RD(sext_xlen(rv_div(lhs, rhs)));
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 31d7585..30225fb 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -4,4 +4,4 @@ reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
-  WRITE_RD(sext_xlen(lhs / rhs));
+  WRITE_RD(sext_xlen(rv_div(lhs, rhs)));
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index e127619..2fba815 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -5,4 +5,4 @@ reg_t rhs = zext32(RS2);
 if(rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
-  WRITE_RD(sext32(lhs / rhs));
+  WRITE_RD(sext32(rv_div(lhs, rhs)));
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 11be17e..f8b4785 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -5,4 +5,4 @@ sreg_t rhs = sext32(RS2);
 if(rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
-  WRITE_RD(sext32(lhs / rhs));
+  WRITE_RD(sext32(rv_div(lhs, rhs)));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index f883a7b..603defe 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -227,3 +227,13 @@ reg_t sv_proc_t::rv_sub(reg_t lhs, reg_t rhs)
     return lhs - rhs;
 }
 
+sreg_t sv_proc_t::rv_div(sreg_t lhs, sreg_t rhs)
+{
+    return lhs / rhs;
+}
+
+reg_t sv_proc_t::rv_div(reg_t lhs, reg_t rhs)
+{
+    return lhs / rhs;
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 05faf61..6a029bb 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -96,6 +96,8 @@ public:
 
     reg_t rv_add(reg_t lhs, reg_t rhs);
     reg_t rv_sub(reg_t lhs, reg_t rhs);
+    reg_t rv_div(reg_t lhs, reg_t rhs);
+    sreg_t rv_div(sreg_t lhs, sreg_t rhs);
 
 #include "sv_insn_decl.h"
 };