From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Apr 2021 15:36:46 +0000 (+0100)
Subject: add crypto-router page start
X-Git-Tag: DRAFT_SVP64_0_1~1064
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=061dc8c8946db7664c603aa84c02d3d2976cba4e;p=libreriscv.git

add crypto-router page start
---

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
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index 000000000..cd6524927
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+++ b/crypto_router_asic.mdwn
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+# Crypto-router ASIC
+
+* NLnet page: [[nlnet_2021_crypto_router]]
+* Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+
+# Specifications:
+
+All of these are entirely Libre-Licensed:
+
+* 300 mhz single-core, Libre-SOC OpenPOWER CPU
+* 180/130 nm (TBD)
+* 5x [[RGMII]] Gigabit Ethernet PHYs
+* 2x USB [[ULPI]] PHYs
+* Direct DMA interface (independent bulk transfer)
+* JTAG, GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
+* On-board Dual-ported SRAM (for Packet Buffers)
+* Opencores [[sdram]]
+* Wishbone interfaces to all peripherals
+* XICS ICP / ICS Interrupt Controller
+
+# Example packet transfer:
+
+* Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
+* Packet is **directly** stored in internal (dual-ported SRAM) by
+  the RGMII PHY itself
+* Interrupt notification is sent to the processor (XICS)
+* Processor inspects packet over Wishbone interface directly
+  connected to 2nd SRAM port.
+* Processor computes, based on decoding the ETH Frame, where the
+  packet must be sent to (which other RGM-II port: e.g. Port 2)
+* Processor initiates Memory-to-Memory DMA transfer
+* DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
+  from one on-board SRAM to the target on-board SRAM associated with Port 2.
+* DMA Engine generates interrupt (XICS) to the CPU to say it is completed
+* Processor notifies target RGM-II PHY to activate "send" of frame out
+  through target RGM-II port 2.
+