From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 26 Nov 2012 18:32:56 +0000 (+0100)
Subject: sram: do not use MemoryPort
X-Git-Tag: 24jan2021_ls180~3073
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0620e75cb8af6de67abee43114a469955ec8fbdf;p=litex.git

sram: do not use MemoryPort
---

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
index f1f74439..7f0cfcb6 100644
--- a/milkymist/sram/__init__.py
+++ b/milkymist/sram/__init__.py
@@ -7,14 +7,18 @@ class SRAM:
 		self.depth = depth
 	
 	def get_fragment(self):
+		# memory
+		mem = Memory(32, self.depth)
+		port = mem.get_port(write_capable=True, we_granularity=8)
 		# generate write enable signal
-		we = Signal(BV(4))
-		comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
+		comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
 			for i in range(4)]
-		# split address
-		nbits = bits_for(self.depth-1)
-		partial_adr = Signal(BV(nbits))
-		comb.append(partial_adr.eq(self.bus.adr[:nbits]))
+		# address and data
+		comb += [
+			port.adr.eq(self.bus.adr[:len(port.adr)]),
+			port.dat_w.eq(self.bus.dat_w),
+			self.bus.dat_r.eq(port.dat_r)
+		]
 		# generate ack
 		sync = [
 			self.bus.ack.eq(0),
@@ -22,6 +26,4 @@ class SRAM:
 				self.bus.ack.eq(1)
 			)
 		]
-		# memory
-		port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
-		return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
+		return Fragment(comb, sync, memories=[mem])