From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 11:44:13 +0000 (+0100)
Subject: get litex sim to kick off a "STEP" via the DMI interface every N cycles
X-Git-Tag: semi_working_ecp5~455
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06231befc456f8dc9fcc2d46c30aea0dc3e88b45;p=soc.git

get litex sim to kick off a "STEP" via the DMI interface every N cycles
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 50ab2a98..d9046f75 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -47,8 +47,8 @@ class LibreSoCSim(SoCCore):
         # setup running of DMI FSM
         dmi_addr = Signal(3)
         dmi_din = Signal(64)
-        dmi_wen = Signal(64)
         dmi_dout = Signal(64)
+        dmi_wen = Signal(1)
         dmi_req = Signal(1)
 
         uptime = Signal(64)
@@ -69,10 +69,6 @@ class LibreSoCSim(SoCCore):
                  self.cpu.dmi_wr.eq(1),    # DMI write
                  If(self.cpu.dmi_ack,
                     (NextState("IDLE"),
-                     self.cpu.dmi_addr.eq(0),
-                     self.cpu.dmi_din.eq(0),
-                     self.cpu.dmi_req.eq(0),
-                     self.cpu.dmi_wr.eq(0),
                     )
                  ),
                 ),
@@ -81,11 +77,15 @@ class LibreSoCSim(SoCCore):
 
         dmifsm.act("IDLE",
             (NextValue(dmi_req, 0),
+             NextValue(dmi_addr, 0),
+             NextValue(dmi_din, 0),
+             NextValue(dmi_wen, 0),
+             NextState("START"), # back to start on next cycle
             )
         )
 
         # kick off a "stop"
-        self.comb += If(uptime == 0,
+        self.sync += If(uptime == 0,
             (dmi_addr.eq(0), # CTRL
              dmi_din.eq(1<<0), # STOP
              dmi_req.eq(1),
@@ -93,6 +93,18 @@ class LibreSoCSim(SoCCore):
             )
         )
 
+        # loop every 1<<N cycles
+        cyclewid = 7
+
+        # kick off a "step"
+        self.sync += If(uptime[0:cyclewid] == 4,
+            (dmi_addr.eq(0), # CTRL
+             dmi_din.eq(1<<3), # STEP
+             dmi_req.eq(1),
+             dmi_wen.eq(1),
+            )
+        )
+
         # monitor ibus write
         self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
                         self.cpu.ibus.we,