From: lkcl <lkcl@web>
Date: Wed, 8 Jun 2022 23:44:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1905
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=062bfbe9ff4d22fad2ddf7931b6a2263d1581ada;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index adadccb21..65c794468 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -18,6 +18,13 @@ To achieve full soft-emulated interoperability, all implementations
 all SPRs including all reserved SPRs, all SVP64-related Context
 instructions (REMAP), as well as for the entire SVP64 Prefix space.
 
+*Even if the Power ISA Scalar Specification states that a given
+Scalar
+instruction need not or must not raise an illegal instruction on UNDEFINED
+behaviour, unimiplemented parts of SVP64 *MUST* raise an illegal
+instruction trap when (and only when)
+that same Scalar instruction is Prefixed*.
+
 Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE