From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 4 Jun 2020 09:54:15 +0000 (+0200)
Subject: Add dram core as submodule
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06321976a7dc0535bcfa42f7e3d7dbb53ec14977;p=gram.git

Add dram core as submodule
---

diff --git a/examples/ecpix5.py b/examples/ecpix5.py
index ddc8bf3..7bf866b 100644
--- a/examples/ecpix5.py
+++ b/examples/ecpix5.py
@@ -165,6 +165,7 @@ class DDR3SoC(CPUSoC, Elaboratable):
 		m.submodules.timer   = self.timer
 		m.submodules.intc    = self.intc
 		m.submodules.ddrphy  = self.ddrphy
+		m.submodules.dramcore = self.dramcore
 
 		m.submodules.sysclk = SysClocker()