From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Tue, 10 Sep 2013 09:06:56 +0000 (-0700)
Subject: Add rd field to JAL; drop J
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0642f4db9295a8f96354cdb27432484904ff4214;p=riscv-isa-sim.git

Add rd field to JAL; drop J
---

diff --git a/riscv/decode.h b/riscv/decode.h
index 1529927..2a53f3c 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -82,12 +82,6 @@ struct btype_t
   signed immhi : IMM_BITS-IMMLO_BITS;
 };
 
-struct jtype_t
-{
-  unsigned jump_opcode : OPCODE_BITS;
-  signed target : TARGET_BITS;
-};
-
 struct rtype_t
 {
   unsigned opcode : OPCODE_BITS;
@@ -101,7 +95,7 @@ struct rtype_t
 struct ltype_t
 {
   unsigned opcode : OPCODE_BITS;
-  unsigned bigimm : BIGIMM_BITS;
+  signed bigimm : BIGIMM_BITS;
   unsigned rd : XPRID_BITS;
 };
 
@@ -119,7 +113,6 @@ struct ftype_t
 union insn_t
 {
   itype_t itype;
-  jtype_t jtype;
   rtype_t rtype;
   btype_t btype;
   ltype_t ltype;
@@ -172,7 +165,6 @@ private:
 #define RS1 p->get_state()->XPR[insn.rtype.rs1]
 #define RS2 p->get_state()->XPR[insn.rtype.rs2]
 #define RD p->get_state()->XPR.write_port(insn.rtype.rd)
-#define RA p->get_state()->XPR.write_port(1)
 #define FRS1 p->get_state()->FPR[insn.ftype.rs1]
 #define FRS2 p->get_state()->FPR[insn.ftype.rs2]
 #define FRS3 p->get_state()->FPR[insn.ftype.rs3]
@@ -182,9 +174,8 @@ private:
 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 #define SHAMT (insn.itype.imm12 & 0x3F)
 #define SHAMTW (insn.itype.imm12 & 0x1F)
-#define TARGET insn.jtype.target
 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
+#define JUMP_TARGET (pc + (BIGIMM << JUMP_ALIGN_BITS))
 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
 #define RM ({ int rm = insn.ftype.rm; \
diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 105df75..703b5a6 100644
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -273,7 +273,7 @@ class jump_target_t : public arg_t
   virtual std::string to_string(insn_t insn) const
   {
     std::stringstream s;
-    int32_t target = (int32_t)insn.jtype.target;
+    int32_t target = (int32_t)insn.ltype.bigimm;
     target <<= JUMP_ALIGN_BITS;
     char sign = target >= 0 ? '+' : '-';
     s << "pc " << sign << std::hex << " 0x" << abs(target);
@@ -426,7 +426,7 @@ disassembler::disassembler()
   #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg, branch_target)
   #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, branch_target)
   #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, xrs1_reg, branch_target)
-  #define DEFINE_JTYPE(code) DISASM_INSN(#code, code, 0, jump_target)
+  #define DEFINE_JTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, jump_target)
   #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, xrd_reg, load_address)
   #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, xrs2_reg, store_address)
   #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, xrd_reg, xrs2_reg, amo_address)
@@ -479,7 +479,6 @@ disassembler::disassembler()
   DEFINE_FSTORE(fsw)
   DEFINE_FSTORE(fsd)
 
-  DEFINE_JTYPE(j);
   DEFINE_JTYPE(jal);
 
   DEFINE_B0TYPE("b",    beq);
diff --git a/riscv/insns/j.h b/riscv/insns/j.h
deleted file mode 100644
index 3a4da2a..0000000
--- a/riscv/insns/j.h
+++ /dev/null
@@ -1 +0,0 @@
-set_pc(JUMP_TARGET);
diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h
index 41dc403..9caac55 100644
--- a/riscv/insns/jal.h
+++ b/riscv/insns/jal.h
@@ -1,2 +1,2 @@
-RA = npc;
+RD = npc;
 set_pc(JUMP_TARGET);
diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 5e366cd..8b0c5e3 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -1,7 +1,7 @@
 DECLARE_INSN(fmv_s_x, 0x1e053, 0x3fffff)
 DECLARE_INSN(remuw, 0x7bb, 0x1ffff)
 DECLARE_INSN(fmin_d, 0x180d3, 0x1ffff)
-DECLARE_INSN(lr_w, 0x1012b, 0x3fffff)
+DECLARE_INSN(lr_w, 0x412b, 0x3e7fff)
 DECLARE_INSN(bltu, 0x363, 0x3ff)
 DECLARE_INSN(fmin_s, 0x18053, 0x1ffff)
 DECLARE_INSN(slliw, 0x9b, 0x3f83ff)
@@ -26,22 +26,22 @@ DECLARE_INSN(mtpcr, 0x73, 0x1ffff)
 DECLARE_INSN(break, 0xf7, 0xffffffff)
 DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff)
 DECLARE_INSN(mul, 0x433, 0x1ffff)
-DECLARE_INSN(amominu_d, 0x19ab, 0x1ffff)
+DECLARE_INSN(amominu_d, 0x19ab, 0x7fff)
 DECLARE_INSN(srli, 0x293, 0x3f03ff)
-DECLARE_INSN(amominu_w, 0x192b, 0x1ffff)
+DECLARE_INSN(amominu_w, 0x192b, 0x7fff)
 DECLARE_INSN(divuw, 0x6bb, 0x1ffff)
 DECLARE_INSN(mulw, 0x43b, 0x1ffff)
 DECLARE_INSN(srlw, 0x2bb, 0x1ffff)
 DECLARE_INSN(div, 0x633, 0x1ffff)
-DECLARE_INSN(j, 0x6b, 0x7f)
-DECLARE_INSN(fence, 0x12f, 0x3ff)
+DECLARE_INSN(fdiv_d, 0x30d3, 0x1f1ff)
+DECLARE_INSN(fence, 0x2f, 0x1ff)
 DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff)
 DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff)
 DECLARE_INSN(fle_s, 0x17053, 0x1ffff)
-DECLARE_INSN(fence_v_l, 0x22f, 0x3ff)
+DECLARE_INSN(fence_v_l, 0x12f, 0x1ff)
 DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff)
 DECLARE_INSN(fle_d, 0x170d3, 0x1ffff)
-DECLARE_INSN(fence_i, 0xaf, 0x3ff)
+DECLARE_INSN(fence_i, 0xaf, 0x1ff)
 DECLARE_INSN(fnmsub_d, 0xcb, 0x1ff)
 DECLARE_INSN(addw, 0x3b, 0x1ffff)
 DECLARE_INSN(sll, 0xb3, 0x1ffff)
@@ -49,7 +49,7 @@ DECLARE_INSN(xor, 0x233, 0x1ffff)
 DECLARE_INSN(sub, 0x10033, 0x1ffff)
 DECLARE_INSN(eret, 0x273, 0xffffffff)
 DECLARE_INSN(blt, 0x263, 0x3ff)
-DECLARE_INSN(sc_w, 0x1052b, 0x1ffff)
+DECLARE_INSN(sc_w, 0x452b, 0x7fff)
 DECLARE_INSN(rem, 0x733, 0x1ffff)
 DECLARE_INSN(srliw, 0x29b, 0x3f83ff)
 DECLARE_INSN(lui, 0x37, 0x7f)
@@ -58,7 +58,7 @@ DECLARE_INSN(addi, 0x13, 0x3ff)
 DECLARE_INSN(mulh, 0x4b3, 0x1ffff)
 DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff)
 DECLARE_INSN(srai, 0x10293, 0x3f03ff)
-DECLARE_INSN(amoand_d, 0x9ab, 0x1ffff)
+DECLARE_INSN(amoand_d, 0x9ab, 0x7fff)
 DECLARE_INSN(flt_d, 0x160d3, 0x1ffff)
 DECLARE_INSN(sraw, 0x102bb, 0x1ffff)
 DECLARE_INSN(fmul_d, 0x20d3, 0x1f1ff)
@@ -66,7 +66,7 @@ DECLARE_INSN(ld, 0x183, 0x3ff)
 DECLARE_INSN(ori, 0x313, 0x3ff)
 DECLARE_INSN(flt_s, 0x16053, 0x1ffff)
 DECLARE_INSN(addiw, 0x1b, 0x3ff)
-DECLARE_INSN(amoand_w, 0x92b, 0x1ffff)
+DECLARE_INSN(amoand_w, 0x92b, 0x7fff)
 DECLARE_INSN(feq_s, 0x15053, 0x1ffff)
 DECLARE_INSN(fsgnjx_d, 0x70d3, 0x1ffff)
 DECLARE_INSN(sra, 0x102b3, 0x1ffff)
@@ -82,10 +82,9 @@ DECLARE_INSN(rdinstret, 0xa77, 0x7ffffff)
 DECLARE_INSN(fcvt_wu_d, 0xb0d3, 0x3ff1ff)
 DECLARE_INSN(subw, 0x1003b, 0x1ffff)
 DECLARE_INSN(fmax_s, 0x19053, 0x1ffff)
-DECLARE_INSN(amomaxu_d, 0x1dab, 0x1ffff)
+DECLARE_INSN(amomaxu_d, 0x1dab, 0x7fff)
 DECLARE_INSN(xori, 0x213, 0x3ff)
-DECLARE_INSN(fdiv_d, 0x30d3, 0x1f1ff)
-DECLARE_INSN(amomaxu_w, 0x1d2b, 0x1ffff)
+DECLARE_INSN(amomaxu_w, 0x1d2b, 0x7fff)
 DECLARE_INSN(fcvt_wu_s, 0xb053, 0x3ff1ff)
 DECLARE_INSN(rdtime, 0x677, 0x7ffffff)
 DECLARE_INSN(andi, 0x393, 0x3ff)
@@ -97,25 +96,25 @@ DECLARE_INSN(jal, 0x6f, 0x7f)
 DECLARE_INSN(lwu, 0x303, 0x3ff)
 DECLARE_INSN(fmv_x_d, 0x1c0d3, 0x3fffff)
 DECLARE_INSN(fnmadd_d, 0xcf, 0x1ff)
-DECLARE_INSN(amoadd_d, 0x1ab, 0x1ffff)
-DECLARE_INSN(lr_d, 0x101ab, 0x3fffff)
+DECLARE_INSN(amoadd_d, 0x1ab, 0x7fff)
+DECLARE_INSN(lr_d, 0x41ab, 0x3e7fff)
 DECLARE_INSN(fcvt_w_s, 0xa053, 0x3ff1ff)
 DECLARE_INSN(mulhsu, 0x533, 0x1ffff)
-DECLARE_INSN(amoadd_w, 0x12b, 0x1ffff)
+DECLARE_INSN(amoadd_w, 0x12b, 0x7fff)
 DECLARE_INSN(fcvt_d_lu, 0xd0d3, 0x3ff1ff)
-DECLARE_INSN(amomax_d, 0x15ab, 0x1ffff)
+DECLARE_INSN(amomax_d, 0x15ab, 0x7fff)
 DECLARE_INSN(fsd, 0x1a7, 0x3ff)
 DECLARE_INSN(fcvt_w_d, 0xa0d3, 0x3ff1ff)
 DECLARE_INSN(slt, 0x133, 0x1ffff)
 DECLARE_INSN(sllw, 0xbb, 0x1ffff)
-DECLARE_INSN(amoor_d, 0xdab, 0x1ffff)
+DECLARE_INSN(amoor_d, 0xdab, 0x7fff)
 DECLARE_INSN(slti, 0x113, 0x3ff)
 DECLARE_INSN(remu, 0x7b3, 0x1ffff)
 DECLARE_INSN(flw, 0x107, 0x3ff)
 DECLARE_INSN(remw, 0x73b, 0x1ffff)
 DECLARE_INSN(sltu, 0x1b3, 0x1ffff)
 DECLARE_INSN(slli, 0x93, 0x3f03ff)
-DECLARE_INSN(amoor_w, 0xd2b, 0x1ffff)
+DECLARE_INSN(amoor_w, 0xd2b, 0x7fff)
 DECLARE_INSN(beq, 0x63, 0x3ff)
 DECLARE_INSN(fld, 0x187, 0x3ff)
 DECLARE_INSN(fsub_s, 0x1053, 0x1f1ff)
@@ -124,28 +123,28 @@ DECLARE_INSN(fmv_d_x, 0x1e0d3, 0x3fffff)
 DECLARE_INSN(lbu, 0x203, 0x3ff)
 DECLARE_INSN(syscall, 0x77, 0xffffffff)
 DECLARE_INSN(fsgnj_s, 0x5053, 0x1ffff)
-DECLARE_INSN(amomax_w, 0x152b, 0x1ffff)
+DECLARE_INSN(amomax_w, 0x152b, 0x7fff)
 DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff)
 DECLARE_INSN(mulhu, 0x5b3, 0x1ffff)
-DECLARE_INSN(fence_v_g, 0x2af, 0x3ff)
+DECLARE_INSN(fence_v_g, 0x1af, 0x1ff)
 DECLARE_INSN(fssr, 0x1f053, 0x3fffff)
 DECLARE_INSN(setpcr, 0x173, 0x3ff)
 DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff)
 DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff)
 DECLARE_INSN(auipc, 0x17, 0x7f)
 DECLARE_INSN(fcvt_lu_d, 0x90d3, 0x3ff1ff)
-DECLARE_INSN(sc_d, 0x105ab, 0x1ffff)
+DECLARE_INSN(sc_d, 0x45ab, 0x7fff)
 DECLARE_INSN(fmadd_s, 0x43, 0x1ff)
 DECLARE_INSN(fsqrt_s, 0x4053, 0x3ff1ff)
-DECLARE_INSN(amomin_w, 0x112b, 0x1ffff)
+DECLARE_INSN(amomin_w, 0x112b, 0x7fff)
 DECLARE_INSN(fsgnjn_s, 0x6053, 0x1ffff)
-DECLARE_INSN(amoswap_d, 0x5ab, 0x1ffff)
+DECLARE_INSN(amoswap_d, 0x5ab, 0x7fff)
 DECLARE_INSN(fsqrt_d, 0x40d3, 0x3ff1ff)
 DECLARE_INSN(fmadd_d, 0xc3, 0x1ff)
 DECLARE_INSN(divw, 0x63b, 0x1ffff)
-DECLARE_INSN(amomin_d, 0x11ab, 0x1ffff)
+DECLARE_INSN(amomin_d, 0x11ab, 0x7fff)
 DECLARE_INSN(divu, 0x6b3, 0x1ffff)
-DECLARE_INSN(amoswap_w, 0x52b, 0x1ffff)
+DECLARE_INSN(amoswap_w, 0x52b, 0x7fff)
 DECLARE_INSN(jalr, 0x67, 0x3ff)
 DECLARE_INSN(fadd_s, 0x53, 0x1f1ff)
 DECLARE_INSN(fcvt_l_d, 0x80d3, 0x3ff1ff)
diff --git a/riscv/pcr.h b/riscv/pcr.h
index 8c9617d..8780cdd 100644
--- a/riscv/pcr.h
+++ b/riscv/pcr.h
@@ -45,6 +45,9 @@
 #define IRQ_HOST  6
 #define IRQ_TIMER 7
 
+#define IMPL_SPIKE  1
+#define IMPL_ROCKET 2
+
 #define CAUSE_MISALIGNED_FETCH 0
 #define CAUSE_FAULT_FETCH 1
 #define CAUSE_ILLEGAL_INSTRUCTION 2