From: Jan Beulich Date: Wed, 15 Nov 2017 07:48:51 +0000 (+0100) Subject: x86-64: don't allow use of %axl as accumulator X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0645f0a2a75ad77d9786595978591d3f302f9647;p=binutils-gdb.git x86-64: don't allow use of %axl as accumulator Just like %cxl can't be used as shift count register. Otherwise for consistency %cxl would need to gain "ShiftCount" and use of both ought to properly cause REX prefixes to be emitted. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index f9273938da7..66bc0349052 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,15 @@ +2017-11-15 Jan Beulich + + * testsuite/gas/i386/x86-64-reg.s: Add extended byte reg tests. + * testsuite/gas/i386/x86-64-reg.d, + testsuite/gas/i386/x86-64-reg-intel.d, + testsuite/gas/i386/ilp32/x86-64-reg.d, + testsuite/gas/i386/ilp32/x86-64-reg-intel.d: Adjust + expectations. + + * testsuite/gas/i386/x86-64-reg-bad.{s,l}: New. + * testsuite/gas/i386/i386.exp: Run new test. + 2017-11-14 Jim Wilson * testsuite/gas/lns/lns.exp (lns-common-1): Add riscv*-*-* to alt list. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 1662d9c7b0c..7a8b642432b 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -628,6 +628,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-mem" run_dump_test "x86-64-mem-intel" run_dump_test "x86-64-reg" + run_list_test "x86-64-reg-bad" "-al" run_dump_test "x86-64-reg-intel" run_dump_test "x86-64-sib" run_dump_test "x86-64-sib-intel" diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d index 839df9c5a6f..99d79d5b721 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq xmm10,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq xmm10,0x2 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add al,0x1 +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add cl,0x1 +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add dl,0x1 +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add bl,0x1 +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add spl,0x1 +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add bpl,0x1 +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add sil,0x1 +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add dil,0x1 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2 diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-reg.d b/gas/testsuite/gas/i386/ilp32/x86-64-reg.d index ca17e404041..99e67fbe77a 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-reg.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-reg.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq \$0x2,%xmm10 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq \$0x2,%xmm10 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add \$0x1,%al +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add \$0x1,%cl +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add \$0x1,%dl +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add \$0x1,%bl +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add \$0x1,%spl +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add \$0x1,%bpl +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add \$0x1,%sil +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add \$0x1,%dil [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6 diff --git a/gas/testsuite/gas/i386/x86-64-reg-bad.l b/gas/testsuite/gas/i386/x86-64-reg-bad.l new file mode 100644 index 00000000000..585f1e145f1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-reg-bad.l @@ -0,0 +1,20 @@ +.*: Assembler messages: +.*:6: Error: .* mismatch for `div' +.*:7: Error: .* mismatch for `in' +.*:8: Error: .* mismatch for `lods' +.*:9: Error: .* mismatch for `movabs' +.*:10: Error: .* mismatch for `shl' +GAS LISTING .* + + +[ ]*[1-9][0-9]*[ ]+\# Check %axl / %cxl aren't permitted as accumulator / shift count +[ ]*[1-9][0-9]*[ ]+ +[ ]*[1-9][0-9]*[ ]+\.text +[ ]*[1-9][0-9]*[ ]+reg: +[ ]*[1-9][0-9]*[ ]+\?* 4080C001[ ]+add \$1, %axl +[ ]*[1-9][0-9]*[ ]+div %bl, %axl +[ ]*[1-9][0-9]*[ ]+in %dx, %axl +[ ]*[1-9][0-9]*[ ]+lods \(%rsi\), %axl +[ ]*[1-9][0-9]*[ ]+movabs -1, %axl +[ ]*[1-9][0-9]*[ ]+shl %cxl, %eax +[ ]*[1-9][0-9]*[ ]+\?* 40F6C001[ ]+test \$1, %axl diff --git a/gas/testsuite/gas/i386/x86-64-reg-bad.s b/gas/testsuite/gas/i386/x86-64-reg-bad.s new file mode 100644 index 00000000000..d7e0c7c8e2a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-reg-bad.s @@ -0,0 +1,11 @@ +# Check %axl / %cxl aren't permitted as accumulator / shift count + + .text +reg: + add $1, %axl + div %bl, %axl + in %dx, %axl + lods (%rsi), %axl + movabs -1, %axl + shl %cxl, %eax + test $1, %axl diff --git a/gas/testsuite/gas/i386/x86-64-reg-intel.d b/gas/testsuite/gas/i386/x86-64-reg-intel.d index c04645b10d2..00120b7d267 100644 --- a/gas/testsuite/gas/i386/x86-64-reg-intel.d +++ b/gas/testsuite/gas/i386/x86-64-reg-intel.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq xmm10,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq xmm10,0x2 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add al,0x1 +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add cl,0x1 +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add dl,0x1 +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add bl,0x1 +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add spl,0x1 +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add bpl,0x1 +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add sil,0x1 +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add dil,0x1 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2 diff --git a/gas/testsuite/gas/i386/x86-64-reg.d b/gas/testsuite/gas/i386/x86-64-reg.d index fb560d17f51..292a827cd7b 100644 --- a/gas/testsuite/gas/i386/x86-64-reg.d +++ b/gas/testsuite/gas/i386/x86-64-reg.d @@ -25,6 +25,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq \$0x2,%xmm10 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq \$0x2,%xmm10 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add \$0x1,%al +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add \$0x1,%cl +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add \$0x1,%dl +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add \$0x1,%bl +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add \$0x1,%spl +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add \$0x1,%bpl +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add \$0x1,%sil +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add \$0x1,%dil [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6 diff --git a/gas/testsuite/gas/i386/x86-64-reg.s b/gas/testsuite/gas/i386/x86-64-reg.s index 6dcaba51607..69ac24bc5a4 100644 --- a/gas/testsuite/gas/i386/x86-64-reg.s +++ b/gas/testsuite/gas/i386/x86-64-reg.s @@ -21,6 +21,15 @@ psllq $2, %mm6 psllq $2, %xmm10 pslldq $2, %xmm10 + add $1, %axl + add $1, %cxl + add $1, %dxl + add $1, %bxl + add $1, %spl + add $1, %bpl + add $1, %sil + add $1, %dil + .intel_syntax noprefix psrlw mm6, 2 psrlw xmm2, 2 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 68cbfcc52ba..e8af8b2eda3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-11-15 Jan Beulich + + * i386-reg.tbl (axl): Remove Acc and Byte. + * i386-tbl.h: Re-generate. + 2017-11-14 Jan Beulich * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New. diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index fa9c8564a2d..0c4e796db07 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -29,7 +29,7 @@ ah, Reg8, 0, 4, Dw2Inval, Dw2Inval ch, Reg8, 0, 5, Dw2Inval, Dw2Inval dh, Reg8, 0, 6, Dw2Inval, Dw2Inval bh, Reg8, 0, 7, Dw2Inval, Dw2Inval -axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 85075d66c5d..364bc9789fd 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -101351,7 +101351,7 @@ const reg_entry i386_regtab[] = 0, 7, { Dw2Inval, Dw2Inval } }, { "axl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "cxl",