From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 4 Jan 2015 10:45:39 +0000 (+0100)
Subject: Fixed pattern matching in "hierarchy -generate"
X-Git-Tag: yosys-0.5~137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0648e2874c9823e8b4012877b49dfa6eef3d7034;p=yosys.git

Fixed pattern matching in "hierarchy -generate"
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 66d660324..58b796a62 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct generate_port_decl_t {
 	bool input, output;
-	RTLIL::IdString portname;
+	string portname;
 	int index;
 };
 
@@ -101,7 +101,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 			for (auto &decl : portdecls)
 				if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
 					generate_port_decl_t d = decl;
-					d.portname = portname;
+					d.portname = portname.str();
 					d.index = *indices.begin();
 					log_assert(!indices.empty());
 					indices.erase(d.index);