From: Richard Henderson <rth@redhat.com>
Date: Thu, 20 Jun 2002 23:47:35 +0000 (-0700)
Subject: m68k.md (zero_extendsidi2): Create expander; duplicate pattern and adjust constraints... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0655301f429aca9e91a3d6e7db59e61a47a3fc83;p=gcc.git

m68k.md (zero_extendsidi2): Create expander; duplicate pattern and adjust constraints for coldfire.

        * config/m68k/m68k.md (zero_extendsidi2): Create expander; duplicate
        pattern and adjust constraints for coldfire.

From-SVN: r54865
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4a79b52cd96..13d7ba7d35a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-06-20  Richard Henderson  <rth@redhat.com>
+
+	PR target/4041
+	* config/m68k/m68k.md (zero_extendsidi2): Create expander; duplicate
+	pattern and adjust constraints for coldfire.
+
 2002-06-20  Richard Henderson  <rth@redhat.com>
 
 	* explow.c (probe_stack_range): Use gen_rtx_fmt_ee.
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 35ca2baae55..16b6ca6da86 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1525,10 +1525,40 @@
 }")
 
 ;; this is the canonical form for (lshiftrt:DI x 32)
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-    (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
+(define_expand "zero_extendsidi2"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "")
+    (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
   ""
+  "")
+
+(define_insn "*zero_extendsidi2_cf"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
+    (zero_extend:DI (match_operand:SI 1 "general_operand" "ro,r")))]
+  "TARGET_5200"
+  "*
+{
+  CC_STATUS_INIT;
+  if (GET_CODE (operands[0]) == REG)
+    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    return \"move%.l %1,%0\;clr%.l %0\";
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    return \"clr%.l %0\;move%.l %1,%0\";
+  else
+    operands[2] = adjust_address (operands[0], SImode, 4);
+  if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
+      || REGNO (operands[1]) != REGNO (operands[2]))
+    output_asm_insn (\"move%.l %1,%2\", operands);
+  if (ADDRESS_REG_P (operands[0]))
+    return \"sub%.l %0,%0\";
+  else
+    return \"clr%.l %0\";
+}")
+
+(define_insn "*zero_extendsidi2"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
+    (zero_extend:DI (match_operand:SI 1 "general_operand" "ro")))]
+  "!TARGET_5200"
   "*
 {
   CC_STATUS_INIT;