From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 13 Nov 2018 13:52:48 +0000 (+0000)
Subject: alter set_csr to call get_csr, will make csrrw* easier
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0655ff269db3611e0de73382499889a5b6371b44;p=riscv-isa-sim.git

alter set_csr to call get_csr, will make csrrw* easier
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index fadd194..488a283 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -485,8 +485,9 @@ void state_t::sv_csr_pred_unpack()
     }
 }
 
-void processor_t::set_csr(int which, reg_t val)
+reg_t processor_t::set_csr(int which, reg_t val, bool csrrwi)
 {
+  reg_t old_val = get_csr(which);
   val = _zext_xlen(val);
   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
                        | ((ext != NULL) << IRQ_COP);
@@ -820,6 +821,7 @@ void processor_t::set_csr(int which, reg_t val)
       state.dscratch = val;
       break;
   }
+  return old_val;
 }
 
 reg_t processor_t::get_csr(int which)
diff --git a/riscv/processor.h b/riscv/processor.h
index 0ae0617..4a7fee8 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -220,7 +220,7 @@ public:
   void set_histogram(bool value);
   void reset();
   void step(size_t n); // run for n cycles
-  void set_csr(int which, reg_t val);
+  reg_t set_csr(int which, reg_t val, bool immed=false);
   reg_t get_csr(int which);
 #ifdef SPIKE_SIMPLEV
   sv_mmu_t* get_mmu() { return mmu; }