From: lkcl <lkcl@web>
Date: Fri, 31 Mar 2023 23:27:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~208
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=065647d292e4018a6a1f342bf11d107ee8192251;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 9223fcfa2..32b5ad4eb 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -118,10 +118,9 @@ register-register operations.
 To be absolutely clear:
 
 ```
-    No conceptual arithmetic ordering or other changes over the Scalar
-    Power ISA definitions to registers or register files or to arithmetic
-    or Logical Operations beyond element-width subdivision and sequential
-    element numbering are expressed or implied
+    There are no conceptual arithmetic ordering or other changes over the
+    Scalar Power ISA definitions to registers or register files or to
+    arithmetic or Logical Operations beyond element-width subdivision
 ```
 
 Element offset
@@ -277,21 +276,23 @@ The programmer is expected to be aware however that the full width of
 the entire 64-bit Condition Register is considered to be "an element".
 This is **not** like any other Condition-Register instructions because
 all other CR instructions, on closer investigation, will be observed
-to all be CR-bit or CR-Field related. Thus `VL` of 16 must be used*
+to all be CR-bit or CR-Field related. Thus a `VL` of 16 must be used*
 
 ## Future expansion.
 
 With the way that EXTRA fields are defined and applied to register fields,
 future versions of SV may involve 256 or greater registers. Backwards
 binary compatibility may be achieved with a PCR bit (Program Compatibility
-Register).  Further discussion is out of scope for this version of SVP64.
+Register) or an MSR bit analogous to SF.
+Further discussion is out of scope for this version of SVP64.
 
 Additionally, a future variant of SVP64 will be applied to the Scalar
 (Quad-precision and 128-bit) VSX instructions. Element-width overrides
-are an opportunity to expand the Power ISA to 256-bit, 512-bit and
+are an opportunity to expand a future version of the Power ISA
+to 256-bit, 512-bit and
 1024-bit operations, as well as doubling or quadrupling the number
-of CSX registers to 128 or 256. Again further discussion is out of
-scope for this version of SVP64
+of VSX registers to 128 or 256. Again further discussion is out of
+scope for this version of SVP64.
 
 --------