From: Garret Kelly <Garret.Kelly@gmail.com>
Date: Sat, 21 May 2016 22:41:28 +0000 (-0400)
Subject: htif: catch proper store exception (#44)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=065ad6b114d006fda2d4ca6298c36c31e698b377;p=riscv-isa-sim.git

htif: catch proper store exception (#44)

The sim's debug_mmu will generate a trap_load_access_fault if the load
fails, not a trap_store_access_fault.  This doesn't materially affect
exection, but results in a nicer log message.
---

diff --git a/riscv/htif.cc b/riscv/htif.cc
index 10dd3e2..6e8fee9 100644
--- a/riscv/htif.cc
+++ b/riscv/htif.cc
@@ -66,7 +66,7 @@ void htif_isasim_t::tick_once()
         reg_t addr = (hdr.addr + i) * HTIF_DATA_ALIGN;
         try {
           sim->debug_mmu->store_uint64(addr, buf[i]);
-        } catch (trap_load_access_fault& e) {
+        } catch (trap_store_access_fault& e) {
           fprintf(stderr, "HTIF: attempt to write to illegal address 0x%" PRIx64 "\n", addr);
           exit(-1);
         }