From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 2 Jul 2009 05:10:58 +0000 (-0700)
Subject: ARM: Add a DataOp format so data op definitions can be aggregated.
X-Git-Tag: Calvin_Submission~252
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=065cb5942790b29886a443ef3f29b2b500231892;p=gem5.git

ARM: Add a DataOp format so data op definitions can be aggregated.
---

diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 1748a09ea..11ba1519f 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -57,6 +57,20 @@ def template PredOpExecute {{
     }
 }};
 
+def template DataDecode {{
+    if (machInst.opcode4 == 0) {
+        if (machInst.sField == 0)
+            return new %(class_name)sImm(machInst);
+        else
+            return new %(class_name)sImmCc(machInst);
+    } else {
+        if (machInst.sField == 0)
+            return new %(class_name)s(machInst);
+        else
+            return new %(class_name)sCc(machInst);
+    }
+}};
+
 let {{
 
     calcCcCode = '''
@@ -78,6 +92,39 @@ let {{
 
 }};
 
+def format DataOp(code, icValue, ivValue) {{
+    code += "resTemp = resTemp;"
+    regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \
+                              shift, Cpsr<29:0>)', code)
+    immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \
+                              shift, Cpsr<29:0>)', code)
+    regIop = InstObjParams(name, Name, 'PredIntOp',
+                           {"code": regCode,
+                            "predicate_test": predicateTest})
+    immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
+                           {"code": immCode,
+                            "predicate_test": predicateTest})
+    regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
+                             {"code": regCode + calcCcCode % vars(),
+                              "predicate_test": predicateTest})
+    immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
+                             {"code": immCode + calcCcCode % vars(),
+                              "predicate_test": predicateTest})
+    header_output = BasicDeclare.subst(regIop) + \
+                    BasicDeclare.subst(immIop) + \
+                    BasicDeclare.subst(regCcIop) + \
+                    BasicDeclare.subst(immCcIop)
+    decoder_output = BasicConstructor.subst(regIop) + \
+                     BasicConstructor.subst(immIop) + \
+                     BasicConstructor.subst(regCcIop) + \
+                     BasicConstructor.subst(immCcIop)
+    exec_output = PredOpExecute.subst(regIop) + \
+                  PredOpExecute.subst(immIop) + \
+                  PredOpExecute.subst(regCcIop) + \
+                  PredOpExecute.subst(immCcIop)
+    decode_block = DataDecode.subst(regIop)
+}};
+
 def format PredOp(code, *opt_flags) {{
     iop = InstObjParams(name, Name, 'PredOp',
                         {"code": code,