From: lkcl <lkcl@web>
Date: Tue, 19 Apr 2022 18:34:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2686
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06676bea51e3ec2e2d5b1204c04a1e8571e7008c;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index ac271714b..27d6981e8 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -103,6 +103,27 @@ that, just as with repeated chained application of `addeo`, macro-op
 fusion may be internally applied to a sequence of these strange multiply
 operations. Such a trick works equally as well in Scalar-only.
 
+**Application of SVP64**
+
+SVP64 has the means to re-target in-out registers that would normally
+be forced to be an overwrite.  Examples include `ldu` which, ordinarily,
+in Scalar v3.0B, has RA overwritten.  `sv.ldu` on the other hand permits
+limited range re-targetting, by applying one EXTRA bit to RA-as-a-source
+and a *separate* bit to RA-as-a-destination.
+
+If applied to this new 3-in 2-out mul-and-add operation it not only
+becomes possible to set RC as either scalar or vector, it becomes
+possible to stop RC from being overwritten.
+
+    product = RA*RB+RC      # RC sourced as Vector
+    RT = lowerhalf(product) # Vector destination
+    RC = upperhalf(product) # Vector destination
+
+Where previously this instruction had limited specialist applicability
+for big-integer multiply, because RC could only be utilised as a
+64-bit Carry, the possibility for RC to be a Vector greatly
+expands its potential.
+
 ## Divide
 
 The simplest implementation of big-int divide is the standard schoolbook