From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 09:14:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~556
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=067fec0b572dea1564a0afc95ac9624466745ef9;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index a4e81e2d8..168a1995a 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -741,12 +741,12 @@ For modes:
 /// `temp_pred` is a user-visible Vector Condition register 
 ///
 /// all input arrays have length `vl`
-pub fn reduce(  vl,  input_vec, temp_vec, input_pred, temp_pred,):
+def reduce(  vl,  input_vec, temp_vec, input_pred, temp_pred,):
     for i in 0..vl
         temp_pred[i] = input_pred[i];
         if temp_pred[i]
             temp_vec[i] = input_vec[i]
-    mut step = 1;
+    step = 1;
     while step < vl
         step *= 2;
         for i in (0..vl).step_by(step)