From: Marek Olšák <marek.olsak@amd.com>
Date: Wed, 24 Jul 2019 02:32:02 +0000 (-0400)
Subject: radeonsi: fix DAL hang due to incorrect DCC offset on Raven
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=068093e84c52238102c62e5392fcda9b9204a297;p=mesa.git

radeonsi: fix DAL hang due to incorrect DCC offset on Raven

Set the correct relative offset.

Fixes: f8b6c5a "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support"
---

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 111607be333..904a39b6fed 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -708,7 +708,28 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
 	/* Clear the base address and set the relative DCC offset. */
 	desc[0] = 0;
 	desc[1] &= C_008F14_BASE_ADDRESS_HI;
-	desc[7] = tex->dcc_offset >> 8;
+
+	switch (sscreen->info.chip_class) {
+	case GFX6:
+	case GFX7:
+		break;
+	case GFX8:
+		desc[7] = tex->dcc_offset >> 8;
+		break;
+	case GFX9:
+		desc[7] = tex->dcc_offset >> 8;
+		desc[5] &= C_008F24_META_DATA_ADDRESS;
+		desc[5] |= S_008F24_META_DATA_ADDRESS(tex->dcc_offset >> 40);
+		break;
+	case GFX10:
+		desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
+		desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->dcc_offset >> 8);
+		desc[7] = tex->dcc_offset >> 16;
+		break;
+	default:
+		assert(0);
+	}
+
 
 	/* Dwords [2:9] contain the image descriptor. */
 	memcpy(&md.metadata[2], desc, sizeof(desc));