From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 18 Mar 2022 12:32:42 +0000 (+0000)
Subject: whitespace / module-import / comments / tidyup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0683187413a645310631d0e250198e0f5b2e441f;p=ls2.git

whitespace / module-import / comments / tidyup
---

diff --git a/src/ls2.py b/src/ls2.py
index 2a3e819..6ce9a73 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -14,9 +14,13 @@ from nmigen.cli import verilog
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
 from nmigen_soc.memory import MemoryMap
+from nmigen.utils import log2_int
 
 from nmigen_stdio.serial import AsyncSerial
+
+# HyperRAM
 from nmigen_boards.resources.memory import HyperRAMResource
+from lambdasoc.periph.hyperram import HyperRAM
 
 from lambdasoc.periph.intc import GenericInterruptController
 from lambdasoc.periph.sram import SRAMPeripheral
@@ -29,22 +33,23 @@ from soc.bus.external_core import ExternalCore # external libresoc/microwatt
 from soc.bus.wb_downconvert import WishboneDownConvert
 from soc.bus.syscon import MicrowattSYSCON
 
+# DDR3
 from gram.common import (PhySettings, get_cl_cw, get_sys_latency,
                         get_sys_phases,)
-from nmigen.utils import log2_int
 from gram.core import gramCore
 from gram.phy.ecp5ddrphy import ECP5DDRPHY
 from gram.phy.fakephy import FakePHY, SDRAM_VERBOSE_STD, SDRAM_VERBOSE_DBG
 from gram.modules import MT41K256M16, MT41K64M16
 from gram.frontend.wishbone import gramWishbone
 
+# Board (and simulation) platforms
 from nmigen_boards.versa_ecp5 import VersaECP5Platform
 from nmigen_boards.ulx3s import ULX3S_85F_Platform
 from nmigen_boards.arty_a7 import ArtyA7_100Platform
 from nmigen_boards.test.blinky import Blinky
-
-from crg import ECPIX5CRG
 from icarusversa import IcarusVersaPlatform
+# Clock-Reset Generator (works for all ECP5 platforms)
+from crg import ECPIX5CRG
 
 import sys
 import os
@@ -228,7 +233,7 @@ class DDR3SoC(SoC, Elaboratable):
                  firmware=None,
                  spi0_addr, spi0_cfg_addr,
                  hyperram_addr=None,
-                 hyperram_pinset=None,
+                 hyperram_pins=None,
                  clk_freq=50e6,
                  add_cpu=True):
 
@@ -398,7 +403,8 @@ class DDR3SoC(SoC, Elaboratable):
             self._decoder.add(self.spi0.cfg_bus, addr=spi0_cfg_addr)
 
         # HyperRAM modules *plural*. Assumes using a Quad PMOD by Piotr
-        # Esden, sold by 1bitsquared
+        # Esden, sold by 1bitsquared, only doing one CS_N enable at the
+        # moment
 
         self.memory_map = self._decoder.bus.memory_map
 
@@ -596,15 +602,15 @@ if __name__ == "__main__":
                                         dir={"dq":"io", "cs_n":"o", "clk":"o"},
                                         xdr={"dq": 1, "cs_n": 1, "clk": 0})
 
-    # Get HyperRAM pinsets, there are multiple of these!
-    hyperram_pinset = None
+    # Get HyperRAM pins
+    hyperram_pins = None
     if platform is not None and fpga in ['versa_ecp5']:
         hyperram_ios = HyperRAMResources(cs_n="B1",
                                          dq="D0 D1 D2 D3 D4 D7 D6 D7",
                                          rwds="B2", rst_n="B3", clk_p="B4",
                                          attrs=IOStandard("LVCMOS33"))
         self.platform.add_extension(hyperram_ios)
-        hyperram_pinset = self.platform.request("hyperram")
+        hyperram_pins = self.platform.request("hyperram")
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
@@ -620,7 +626,7 @@ if __name__ == "__main__":
                   ddr_pins=ddr_pins,
                   uart_pins=uart_pins,
                   spi_0_pins=spi_0_pins,
-                  hyperram_pinset=hyperram_pinset,
+                  hyperram_pins=hyperram_pins,
                   firmware=firmware,
                   clk_freq=clk_freq,
                   add_cpu=True)