From: Adrian Herrera <adrian.herrera@arm.com>
Date: Fri, 14 Feb 2020 09:18:08 +0000 (+0000)
Subject: arch-arm: Fix CNTFRQ_EL0 permission bits
X-Git-Tag: v19.0.0.0~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=068ded195c1656b7b5e2b53efc9722ba0bc0d463;p=gem5.git

arch-arm: Fix CNTFRQ_EL0 permission bits

The register is marked as being writable at EL3 only (mon).  However the
arm arm states the register is accessible at the highest implemented EL.
Which means that if EL1 is the highest EL, EL1 code should be able to
modify the register value.

Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25428
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index c25c24bb7..0b883a122 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3707,8 +3707,9 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_HTPIDR)
       .hyp().monNonSecure();
     InitReg(MISCREG_CNTFRQ)
-      .unverifiable()
-      .reads(1).mon();
+      .reads(1)
+      .highest(system)
+      .privSecureWrite(aarch32EL3);
     InitReg(MISCREG_CNTKCTL)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_CNTP_TVAL)
@@ -4453,7 +4454,9 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges().exceptUserMode()
       .mapsTo(MISCREG_CNTKCTL);
     InitReg(MISCREG_CNTFRQ_EL0)
-      .reads(1).mon()
+      .reads(1)
+      .highest(system)
+      .privSecureWrite(aarch32EL3)
       .mapsTo(MISCREG_CNTFRQ);
     InitReg(MISCREG_CNTPCT_EL0)
       .reads(1)