From: Luke Kenneth Casson Leighton Date: Fri, 19 Oct 2018 08:33:27 +0000 (+0100) Subject: provide sv_reg_t overrides of more functions so that sv_reg_t can be a class X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0693986121f91c69c45c7d823b38bcb7b9438931;p=riscv-isa-sim.git provide sv_reg_t overrides of more functions so that sv_reg_t can be a class --- diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h index 56f5df9..6c52f85 100644 --- a/riscv/insns/c_slli.h +++ b/riscv/insns/c_slli.h @@ -1,3 +1,3 @@ require_extension('C'); -require(rv_lt(insn.rvc_zimm(), sv_sreg_t(xlen))); +require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen))); WRITE_RD(sext_xlen(rv_sl(RVC_RS1, insn.rvc_zimm()))); diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h index beabdb6..9d67625 100644 --- a/riscv/insns/c_srai.h +++ b/riscv/insns/c_srai.h @@ -1,3 +1,3 @@ require_extension('C'); -require(rv_lt(insn.rvc_zimm(), sv_sreg_t(xlen))); +require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen))); WRITE_RVC_RS1S(sext_xlen(rv_sr(sext_xlen(RVC_RS1S), insn.rvc_zimm()))); diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h index 419ee30..7cb790f 100644 --- a/riscv/insns/c_srli.h +++ b/riscv/insns/c_srli.h @@ -1,3 +1,3 @@ require_extension('C'); -require(rv_lt(insn.rvc_zimm(), sv_sreg_t(xlen))); +require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen))); WRITE_RVC_RS1S(sext_xlen(rv_sr(zext_xlen(RVC_RS1S), insn.rvc_zimm()))); diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index c6b01dc..deab217 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -6,6 +6,8 @@ #include "sv.h" #include "decode.h" //#include "sv_reg.h" +typedef reg_t sv_reg_t; + //#include "processor.h" #define REG_RD 0x1 @@ -36,14 +38,18 @@ public: prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp), save_branch_addr(0) {} - uint64_t rvc_imm() { return (insn_t::rvc_imm()); } - uint64_t u_imm() { return (insn_t::u_imm()); } - uint64_t i_imm() { return (insn_t::i_imm()); } - uint64_t s_imm() { return (insn_t::s_imm()); } + sv_reg_t rvc_addi4spn_imm() { return sv_reg_t(insn_t::rvc_addi4spn_imm()); } + sv_reg_t rvc_imm() { return sv_reg_t(insn_t::rvc_imm()); } + sv_reg_t rvc_zimm() { return sv_reg_t(insn_t::rvc_zimm()); } + sv_reg_t rvc_b_imm() { return sv_reg_t(insn_t::rvc_b_imm()); } + sv_reg_t u_imm() { return sv_reg_t(insn_t::u_imm()); } + sv_reg_t i_imm() { return sv_reg_t(insn_t::i_imm()); } + sv_reg_t s_imm() { return sv_reg_t(insn_t::s_imm()); } uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs); uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_lwsp_imm()); } uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_ldsp_imm()); } - uint64_t rvc_swsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_swsp_imm()); } + sv_reg_t rvc_swsp_imm() + { return sv_reg_t(_rvc_spoffs_imm(4, insn_t::rvc_swsp_imm())); } uint64_t rvc_sdsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_sdsp_imm()); } uint64_t rd () { return predicated(_rd (), *offs_rd, prd); }