From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Jul 2020 16:37:23 +0000 (+0200)
Subject: CHANGES: update.
X-Git-Tag: 24jan2021_ls180~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0696b409aba8a44fadda3aff0a23fb6c74aeb694;p=litex.git

CHANGES: update.
---

diff --git a/CHANGES b/CHANGES
index ed4399a7..836fead1 100644
--- a/CHANGES
+++ b/CHANGES
@@ -27,6 +27,7 @@
 	- Revert to a single crt0 (avoid ctr/xip variants).
 	- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
 	- Add AXI-Lite bus standard support.
+	- Add VexRiscv SMP CPU support.
 
 	[> API changes/Deprecation
 	--------------------------