From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 19 Feb 2019 15:27:12 +0000 (+0000)
Subject: reset_less on signals that do not need it
X-Git-Tag: ls180-24jan2020~1865
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06b5f4ac3d397ae96402169c23fdb1bf7eba4c30;p=ieee754fpu.git

reset_less on signals that do not need it
---

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index e6222c2f..8a1287cf 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -12,9 +12,9 @@ class MultiShiftR:
     def __init__(self, width):
         self.width = width
         self.smax = int(log(width) / log(2))
-        self.i = Signal(width)
-        self.s = Signal(self.smax)
-        self.o = Signal(width)
+        self.i = Signal(width, reset_less=True)
+        self.s = Signal(self.smax, reset_less=True)
+        self.o = Signal(width, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -88,9 +88,9 @@ class FPNum:
         self.e_end = self.rmw + self.e_width - 3 # for decoding
 
         self.v = Signal(width)      # Latched copy of value
-        self.m = Signal(m_width)    # Mantissa
-        self.e = Signal((e_width, True)) # Exponent: IEEE754exp+2 bits, signed
-        self.s = Signal()           # Sign bit
+        self.m = Signal(m_width, reset_less=True)    # Mantissa
+        self.e = Signal((e_width, True), reset_less=True) # Exponent: IEEE754exp+2 bits, signed
+        self.s = Signal(reset_less=True)           # Sign bit
 
         self.mzero = Const(0, (m_width, False))
         self.m1s = Const(-1, (m_width, False))
@@ -201,9 +201,9 @@ class FPOp:
     def __init__(self, width):
         self.width = width
 
-        self.v   = Signal(width)
-        self.stb = Signal()
-        self.ack = Signal()
+        self.v   = Signal(width, reset_less=True)
+        self.stb = Signal(reset_less=True)
+        self.ack = Signal(reset_less=True)
 
     def ports(self):
         return [self.v, self.stb, self.ack]
@@ -211,9 +211,9 @@ class FPOp:
 
 class Overflow:
     def __init__(self):
-        self.guard = Signal()     # tot[2]
-        self.round_bit = Signal() # tot[1]
-        self.sticky = Signal()    # tot[0]
+        self.guard = Signal(reset_less=True)     # tot[2]
+        self.round_bit = Signal(reset_less=True) # tot[1]
+        self.sticky = Signal(reset_less=True)    # tot[0]
 
 
 class FPBase:
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index ec4ebb84..fa4166c2 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -30,7 +30,7 @@ class FPADD(FPBase):
         z = FPNum(self.width, False)
 
         w = z.m_width + 4
-        tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
+        tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
 
         of = Overflow()
 
@@ -146,8 +146,8 @@ class FPADD(FPBase):
                     # XXX TODO: the shifter used here is quite expensive
                     # having only one would be better
 
-                    ediff = Signal((len(a.e), True))
-                    ediffr = Signal((len(a.e), True))
+                    ediff = Signal((len(a.e), True), reset_less=True)
+                    ediffr = Signal((len(a.e), True), reset_less=True)
                     m.d.comb += ediff.eq(a.e - b.e)
                     m.d.comb += ediffr.eq(b.e - a.e)
                     with m.If(ediff > 0):