From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Tue, 18 Mar 2014 21:38:07 +0000 (-0700)
Subject: Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06b8f696222948cfa7cbc21b3904da22443a4e0f;p=riscv-isa-sim.git

Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
---

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 5530699..6a56236 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -453,6 +453,10 @@
 #define CSR_UARCH13 0xccd
 #define CSR_UARCH14 0xcce
 #define CSR_UARCH15 0xccf
+#define CSR_COUNTH 0x586
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
 #define CAUSE_MISALIGNED_FETCH 0x0
 #define CAUSE_FAULT_FETCH 0x1
 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
@@ -668,6 +672,10 @@ DECLARE_CSR(uarch12, CSR_UARCH12)
 DECLARE_CSR(uarch13, CSR_UARCH13)
 DECLARE_CSR(uarch14, CSR_UARCH14)
 DECLARE_CSR(uarch15, CSR_UARCH15)
+DECLARE_CSR(counth, CSR_COUNTH)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
 #endif
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
@@ -712,4 +720,8 @@ DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
 DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
 DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
 DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
+DECLARE_CAUSE("counth", CAUSE_COUNTH)
+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
 #endif
diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h
index 8ca7c41..b5d9e48 100644
--- a/riscv/insns/csrrc.h
+++ b/riscv/insns/csrrc.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) & ~RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) & ~RS1)));
diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index fc98056..6c63125 100644
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) & ~(reg_t)insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) & ~(reg_t)insn.rs1())));
diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index 60ac6b3..ba315d4 100644
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), insn.rs1() != 0);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) | RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | RS1)));
diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h
index db6fcd0..827d2d0 100644
--- a/riscv/insns/csrrsi.h
+++ b/riscv/insns/csrrsi.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1())));
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 4b16773..94793e2 100644
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, RS1)));
diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index ff20833..b8ec5f5 100644
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, insn.rs1())));
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 39848b4..f47c8e5 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -233,12 +233,12 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case CSR_EVEC:
       state.evec = val & ~3;
       break;
-    case CSR_CYCLE:
-    case CSR_TIME:
-    case CSR_INSTRET:
     case CSR_COUNT:
       state.count = val;
       break;
+    case CSR_COUNTH:
+      state.count = (val << 32) | (uint32_t)state.count;
+      break;
     case CSR_COMPARE:
       set_interrupt(IRQ_TIMER, false);
       state.compare = val;
@@ -299,6 +299,13 @@ reg_t processor_t::get_pcr(int which)
     case CSR_INSTRET:
     case CSR_COUNT:
       return state.count;
+    case CSR_CYCLEH:
+    case CSR_TIMEH:
+    case CSR_INSTRETH:
+    case CSR_COUNTH:
+      if (rv64)
+        break;
+      return state.count >> 32;
     case CSR_COMPARE:
       return state.compare;
     case CSR_CAUSE:
@@ -327,9 +334,8 @@ reg_t processor_t::get_pcr(int which)
     case CSR_FROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
-    default:
-      throw trap_illegal_instruction();
   }
+  throw trap_illegal_instruction();
 }
 
 void processor_t::set_interrupt(int which, bool on)